From patchwork Fri Mar 23 16:05:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 132351 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp778046ljb; Fri, 23 Mar 2018 09:07:15 -0700 (PDT) X-Google-Smtp-Source: AG47ELs6tECLWpZn7qKTZPOLikTKOx91q9rsDhl0DtG6vJ9QdCg2yfYWTlyLoRS1wqi0DbxuHInG X-Received: by 10.98.97.1 with SMTP id v1mr24824631pfb.119.1521821234877; Fri, 23 Mar 2018 09:07:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521821234; cv=none; d=google.com; s=arc-20160816; b=B4vTLUqceHFoWtzyzZ/2iEulSXoVfTMA2kxvSHZSMEzC+4lrVGh1RJRymvOm8i08c6 6YCV9udb3Lt+A5gAShfqXKQHyybVB1+hljqOF42EY1SFVCpJp0XJdeDKgBO+kC3XvP3N 0AkILiky0lPqjkjN9P+q2Vsvcohc7d95mLB+e/xRCfEue1ExMoAkcmt9lddL/QW28tSt yBTgKL0NOso2BC/yGOq7XtQlzNNeDacA2GcmLecJ1GkZrnb0EhNi9TmSpaeeSnRTjTf+ A6Lk7lQMkgCpDrTK5FMZTYIPEJGzNPB6GozRNy99681kU9POyZVFLOITZNaQr/ytpDPJ px1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=qf0rAdXhdI5kvaceM7y67LsVNSSUVS5SQ6DYrxRxT0A=; b=mx9nA3b8uXSeJ6seWe0kc8hIK8cMUfNo5xJmxriY18TrWEysNdGm0/w72lHcFpuPQ6 g4wJOeLcdZumYcgaDsCr+yQfYgTIxZJeMZ59U1vdPQ5wz5xubcg7/0ogptN5yS75c9dl j23WAXyP0kp5ScrxW9QlqAzktZM//apJSw04tEFy+6PvFGOQJxVSu0I3GFp1yj148PFI Rp4K3aX8+26CDxM5wA8/WUM0DGnSV1SFKEKXb5D1lo7V0/BatEMYWVGzV8q2TwkUFrPm 2jlCbXP1dTwBiUQDCdWEmfuPOTjXea71+R+lfox0rBpt6PV63UtNw0S45Pl4emVbbNLj yzGg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g66si3338643pfc.383.2018.03.23.09.07.14; Fri, 23 Mar 2018 09:07:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752449AbeCWQHL (ORCPT + 28 others); Fri, 23 Mar 2018 12:07:11 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:6689 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752221AbeCWQGL (ORCPT ); Fri, 23 Mar 2018 12:06:11 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id E33C56C81E7A2; Sat, 24 Mar 2018 00:05:50 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Sat, 24 Mar 2018 00:05:44 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 2/8] scsi: hisi_sas: update RAS feature for later revision of v3 HW Date: Sat, 24 Mar 2018 00:05:09 +0800 Message-ID: <1521821115-120040-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521821115-120040-1-git-send-email-john.garry@huawei.com> References: <1521821115-120040-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan There is an modification for later revision of v3 hw. More HW errors are reported through RAS interrupt. These errors were originally reported only through MSI. When report to RAS, some combinations are done to port AXI errors and FIFO OMIT errors. For example, each port has 4 AXI errors, and they are combined to one when report to RAS. This patch does two things. 1. Enable RAS interrupt of these errors and handle them in PCI error handlers. 2. Disable MSI interrupts of these errors for this later revision hw. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 60 ++++++++++++++++++++++++++++++++-- 1 file changed, 58 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 6f3e5ba..df5414a 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -216,6 +216,9 @@ #define SAS_RAS_INTR1 (RAS_BASE + 0x04) #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) +#define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) +#define SAS_RAS_INTR2 (RAS_BASE + 0x20) +#define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) /* HW dma structures */ /* Delivery queue header */ @@ -392,6 +395,7 @@ static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, static void init_reg_v3_hw(struct hisi_hba *hisi_hba) { + struct pci_dev *pdev = hisi_hba->pci_dev; int i; /* Global registers init */ @@ -409,7 +413,10 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); - hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); + if (pdev->revision >= 0x21) + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7fff); + else + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); @@ -428,7 +435,12 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); - hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff87ffff); + if (pdev->revision >= 0x21) + hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, + 0xffffffff); + else + hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, + 0xff87ffff); hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); @@ -503,6 +515,8 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) /* RAS registers init */ hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); + hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); + hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); } static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) @@ -1319,6 +1333,13 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) CHL_INT1); u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); + u32 irq_msk1 = hisi_sas_phy_read32(hisi_hba, phy_no, + CHL_INT1_MSK); + u32 irq_msk2 = hisi_sas_phy_read32(hisi_hba, phy_no, + CHL_INT2_MSK); + + irq_value1 &= ~irq_msk1; + irq_value2 &= ~irq_msk2; if ((irq_msk & (4 << (phy_no * 4))) && irq_value1) { @@ -1448,6 +1469,7 @@ static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + irq_value &= ~irq_msk; for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; @@ -2222,6 +2244,29 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, }; +static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { + { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, + { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, + { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, + { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, + { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, + { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, + { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, + { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, + { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, + { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, + { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, + { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, + { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, + { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, + { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, + { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, + { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, + { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, + { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, + { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, +}; + static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) { struct device *dev = hisi_hba->dev; @@ -2252,6 +2297,17 @@ static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) } hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); + irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); + for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { + ras_error = &sas_ras_intr2_nfe[i]; + if (ras_error->irq_msk & irq_value) { + dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", + ras_error->msg, irq_value); + need_reset = true; + } + } + hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); + return need_reset; }