From patchwork Mon Jul 16 12:57:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre TORGUE X-Patchwork-Id: 142018 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2392728ljj; Mon, 16 Jul 2018 05:58:07 -0700 (PDT) X-Google-Smtp-Source: AAOMgpe+12caGkCXoHRmQmfg2m1jQ6AvrNDEVZaD6fRGxvtggVAbDxtfduqh/gs5CqIELvqEymdv X-Received: by 2002:a62:3a5b:: with SMTP id h88-v6mr17896446pfa.61.1531745887223; Mon, 16 Jul 2018 05:58:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531745887; cv=none; d=google.com; s=arc-20160816; b=IvhL1AhqWkqFTq/X6CAOLXaGC9iHdcHoJ6qyKiyIH/iZRCxAMymhORH5wELy2/IIi8 HClEW+0IybC7NbJIJsW21Z6oQVCWhI4SocXMm9zN8JSZ0Av3X7CrMiC8k/raj9JP0KnL EKyrbM3P36Ek7kg8CzSUvJokPBjMJkpnK4ENC2UKnG9baLVZ3Dho/Jbz8FQv019TnDbc XP+pUKV0ZEUp6rnRO6kv8L9I7VwZxpon0U6OdYvaYu0GjZRDIkKgmON4Im1RGkhjuhfA sRXr+auJ3Ub2NFTD+gC4YZAPmIyG4uFGzWHyhyxNbn487ZZiylMeAqZ2RnZ7iBa6zhdQ 3hzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=fMqd0uG+gpxT/G3Cv8iGJ8DTo4pmUkc2eGhy33GwQYc=; b=ULueZ1/fKVdxvOv2UVWBhQ69JNGif+hEfw9MfJx/LZVzf6Gyt7o1SKMv7PRT9p8uSc 7ZXbwnR5xz9At2Qhyp7QReAhQn4ALsDLCXdtDhZkKxTtlngcFOytUhMlmVSeN4C+JAy6 O5JmCq1SL46pc6dncIiqccENDMPzzNWI99Z65016cHa+wcHRKGyqvpvrSOxSoYF4RIYT nqPjyeudrGlgVHGUC6T8nyZUG2Ud+Xgb5HB9MhVhLDAzcfxwDTJXkBWDu+n1PvWOMhmT ItmMJ/RVI4rM+Rq5yAceDscBvqCiv6DuYUmi3fJHxDQy7oEjW9UK7vEKqi9dt+I9mUfa OqSQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 20-v6si27806378pgl.358.2018.07.16.05.58.06; Mon, 16 Jul 2018 05:58:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729811AbeGPNZX (ORCPT + 31 others); Mon, 16 Jul 2018 09:25:23 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:25073 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729422AbeGPNZW (ORCPT ); Mon, 16 Jul 2018 09:25:22 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w6GCs3Tg030866; Mon, 16 Jul 2018 14:57:41 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2k85recaab-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 16 Jul 2018 14:57:41 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B68CC31; Mon, 16 Jul 2018 12:57:40 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8CF3CE22; Mon, 16 Jul 2018 12:57:40 +0000 (GMT) Received: from localhost (10.75.127.46) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 16 Jul 2018 14:57:40 +0200 From: Alexandre Torgue To: Linus Walleij , Maxime Coquelin , Rob Herring , Mark Rutland CC: , , , , Subject: [PATCH 1/2] pinctrl: stm32: fix bank io port number Date: Mon, 16 Jul 2018 14:57:36 +0200 Message-ID: <1531745857-5561-2-git-send-email-alexandre.torgue@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531745857-5561-1-git-send-email-alexandre.torgue@st.com> References: <1531745857-5561-1-git-send-email-alexandre.torgue@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG3NODE3.st.com (10.75.127.9) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-07-16_04:, , signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In case the exti line is not in line with the bank number (that is the case when there is an hole between two banks, for example GPIOK and then GPIOZ), use "st,bank-ioport" DT property to get the right exti line. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue -- 2.7.4 diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 9a06e1f..60c678a 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -55,6 +55,8 @@ Optional properties: NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller have to use a "gpio-ranges" entry. More details in Documentation/devicetree/bindings/gpio/gpio.txt. + - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line + used to select GPIOs as interrupts). Example 1: #include diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index dfed609..eb6ae14 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -73,6 +73,7 @@ struct stm32_gpio_bank { struct fwnode_handle *fwnode; struct irq_domain *domain; u32 bank_nr; + u32 bank_ioport_nr; }; struct stm32_pinctrl { @@ -298,7 +299,7 @@ static int stm32_gpio_domain_activate(struct irq_domain *d, struct stm32_gpio_bank *bank = d->host_data; struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); - regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr); + regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); return 0; } @@ -948,6 +949,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct device_node *np) { struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; + int bank_ioport_nr; struct pinctrl_gpio_range *range = &bank->range; struct of_phandle_args args; struct device *dev = pctl->dev; @@ -998,12 +1000,17 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[bank_nr].range); } + + if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr)) + bank_ioport_nr = bank_nr; + bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; bank->gpio_chip.ngpio = npins; bank->gpio_chip.of_node = np; bank->gpio_chip.parent = dev; bank->bank_nr = bank_nr; + bank->bank_ioport_nr = bank_ioport_nr; spin_lock_init(&bank->lock); /* create irq hierarchical domain */