From patchwork Wed Aug 15 01:28:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 144257 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp249583ljj; Tue, 14 Aug 2018 18:32:44 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxyQF2HjuHZ+UN+WTXzxAMXjFt/rYWhsQD5Y+Iz2Vgje2UhOCQUa0hT+7GykDKH8Ik4KyAe X-Received: by 2002:a62:a6db:: with SMTP id r88-v6mr25718226pfl.60.1534296764293; Tue, 14 Aug 2018 18:32:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534296764; cv=none; d=google.com; s=arc-20160816; b=vb5nqUKR55D8Py47fukOZYmy9+WqHcpsW3X7xe0hn2mN8jnQtoO1f664OTUsiON/2G R6N5DJ1KlwcWX95BMnzU7KMI3KUpRDFNAAOwDi36QhpqMMigqplLc2Npp2JZlegabYzo uyaF5TByStEg+fWfkvo9ZMWJwLF8wVg2YKGObzrt2+DPpuU4oKamzPOz70szQVBAgoC3 c8ypZgnER0uLEUiEOrR50Q6ofhLVZ4GBKinjS/jPE4So37cwVQkWy7fvniy78JeiZ7Jv 156WJ/s6hX8ezA7ahe723rkjBJ2DmH+PQGBwOoCjRwKNtRx1mfni5pb60I1aij7IiR2g q0uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=zDd6Ka1uRMtFbNXftwIto2qjXK8iAZElSqcNTX7p/wY=; b=KDyBqETQJ5kMrYhTSWamOeLqXkWE0s0WzdYDP/kMN8HuxE0h7Fi2XgAAbkuHbF1+5X K+JoHRfqZWTZapgav+DgKl8Bp8KkURGSrTAOrygGJ2msc1MrbhMSNyuoRxj5eEmAM6LF VvJaNFEgNtxMRJL92HAQjgQdSf2dLOlfBEDgolIWBp9lLEDe/Vk77ajaRT3H2muc/Ixv NzWSxOyqeZo3EH6R+0uKIkkFdmSUfSIS5KpCKdmOixNwVyvSBjAIYgBpCmGEEToXM9y6 oRgwawGNIpt6gwWHs8bl45uQfg2kh1RYFPdh235bm69/eN2SzYpzIYxUS/SW2MFkTU9b lblA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j1-v6si18196866pfh.63.2018.08.14.18.32.44; Tue, 14 Aug 2018 18:32:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728144AbeHOEWd (ORCPT + 32 others); Wed, 15 Aug 2018 00:22:33 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:43501 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725847AbeHOEWc (ORCPT ); Wed, 15 Aug 2018 00:22:32 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 19BC4471CA7EB; Wed, 15 Aug 2018 09:32:38 +0800 (CST) Received: from localhost (10.177.23.164) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.399.0; Wed, 15 Aug 2018 09:32:30 +0800 From: Zhen Lei To: Robin Murphy , Will Deacon , Joerg Roedel , linux-arm-kernel , iommu , linux-kernel CC: Zhen Lei , LinuxArm , Hanjun Guo , Libin , "John Garry" Subject: [PATCH v5 3/5] iommu/io-pgtable-arm: add support for non-strict mode Date: Wed, 15 Aug 2018 09:28:28 +0800 Message-ID: <1534296510-12888-4-git-send-email-thunder.leizhen@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1534296510-12888-1-git-send-email-thunder.leizhen@huawei.com> References: <1534296510-12888-1-git-send-email-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.164] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To support the non-strict mode, now we only tlbi and sync for the strict mode. But for the non-leaf case, always follow strict mode. Signed-off-by: Zhen Lei --- drivers/iommu/io-pgtable-arm.c | 20 ++++++++++++++------ drivers/iommu/io-pgtable.h | 3 +++ 2 files changed, 17 insertions(+), 6 deletions(-) -- 1.8.3 diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index 010a254..20d3e98 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -538,6 +538,7 @@ static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data, phys_addr_t blk_paddr; size_t tablesz = ARM_LPAE_GRANULE(data); size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data); + size_t unmapped = size; int i, unmap_idx = -1; if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) @@ -575,11 +576,16 @@ static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data, tablep = iopte_deref(pte, data); } - if (unmap_idx < 0) - return __arm_lpae_unmap(data, iova, size, lvl, tablep); + if (unmap_idx < 0) { + unmapped = __arm_lpae_unmap(data, iova, size, lvl, tablep); + if (!(data->iop.cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT)) + return unmapped; + } io_pgtable_tlb_add_flush(&data->iop, iova, size, size, true); - return size; + io_pgtable_tlb_sync(&data->iop); + + return unmapped; } static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, @@ -609,7 +615,7 @@ static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, io_pgtable_tlb_sync(iop); ptep = iopte_deref(pte, data); __arm_lpae_free_pgtable(data, lvl + 1, ptep); - } else { + } else if (!(iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT)) { io_pgtable_tlb_add_flush(iop, iova, size, size, true); } @@ -771,7 +777,8 @@ static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg) u64 reg; struct arm_lpae_io_pgtable *data; - if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | IO_PGTABLE_QUIRK_NO_DMA)) + if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | IO_PGTABLE_QUIRK_NO_DMA | + IO_PGTABLE_QUIRK_NON_STRICT)) return NULL; data = arm_lpae_alloc_pgtable(cfg); @@ -863,7 +870,8 @@ static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg) struct arm_lpae_io_pgtable *data; /* The NS quirk doesn't apply at stage 2 */ - if (cfg->quirks & ~IO_PGTABLE_QUIRK_NO_DMA) + if (cfg->quirks & ~(IO_PGTABLE_QUIRK_NO_DMA | + IO_PGTABLE_QUIRK_NON_STRICT)) return NULL; data = arm_lpae_alloc_pgtable(cfg); diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h index 2df7909..beb14a3 100644 --- a/drivers/iommu/io-pgtable.h +++ b/drivers/iommu/io-pgtable.h @@ -71,12 +71,15 @@ struct io_pgtable_cfg { * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a * software-emulated IOMMU), such that pagetable updates need not * be treated as explicit DMA data. + * IO_PGTABLE_QUIRK_NON_STRICT: Put off TLBs invalidation and release + * memory first. */ #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) #define IO_PGTABLE_QUIRK_TLBI_ON_MAP BIT(2) #define IO_PGTABLE_QUIRK_ARM_MTK_4GB BIT(3) #define IO_PGTABLE_QUIRK_NO_DMA BIT(4) + #define IO_PGTABLE_QUIRK_NON_STRICT BIT(5) unsigned long quirks; unsigned long pgsize_bitmap; unsigned int ias;