From patchwork Wed Aug 29 07:03:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145388 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp340090ljw; Wed, 29 Aug 2018 00:03:38 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZGHZjZkdf68hJ5TWvfbzNN98YGw7MCDSxjHtiPSHNTYqFzBP8MBi42ymTjP+/ZX6x2udFn X-Received: by 2002:a65:6309:: with SMTP id g9-v6mr4588670pgv.153.1535526218746; Wed, 29 Aug 2018 00:03:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535526218; cv=none; d=google.com; s=arc-20160816; b=MoZmZ0Lf52eLGRd4j2uzJbuRv4VGg6msil3yBoYLOqan1lW+s9uBTlHSDevyItTdlX DOqq0khSi1YcPJu3wgPVw3GkbnXSKuf1CD+zLsSNVnhW9uJwegiY4Ld77kf84/rwUAtV x+TAa5fYI79Sn6iJrL2Qcem22k/VfIegas94pkLu1xIiacM4y/tilkY21PePQiavOX9W DOXEdbxLgqy4bSHfmR8N2gHkzePaE/+EbigstcbXA4HSS//o8KYd3cvngmMidSnEulLg O+5y2KZ5rUwPenJHsJglksPkjCZLnf2SQZKdGUGLmRPcjLYjt3RPjZ83HXGk0Oxcwd+w WHwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=gVnMBXKc4i1JKgy6ffbRwQOZ0ThpKQAJZ1YKfPm++hw=; b=LG0LiUKOtJ760JFGpnl0nswjXF5v8gFDpvwG7rtoiWl/iN9eaWLJA0C5TnlPu6r5cQ YQcrSxMTTu5cLE9Y6R2XinL/pj7U6bh/eSsS7XLefWECqJaJ/PjEaIDIdrvEzauC1Zu3 0RSVTKyCXdzhVhFKtZiHfOUpe+Jf+taZ4pTsVT+pKIHJ6Ed5jxvLXthZvXfuhCZxjGSz pmI22CAqtDd/JcX9GQ8vfxds3ka/FfJClkpMikfO3wEUKky2U4DF6hYq/SKJ5aiZ5D3z jaTjjEv0VnkuhtuSdkTy3e1VdXd9aYAfdoK6LgLUHtqQz1CdZx/JtMX5aQz0+roJ8c30 r82g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZgS7aX3G; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t64-v6si2959480pgd.176.2018.08.29.00.03.38; Wed, 29 Aug 2018 00:03:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZgS7aX3G; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727749AbeH2K7B (ORCPT + 32 others); Wed, 29 Aug 2018 06:59:01 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:43704 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727172AbeH2K7B (ORCPT ); Wed, 29 Aug 2018 06:59:01 -0400 Received: by mail-pl1-f195.google.com with SMTP id x6-v6so1879566plv.10 for ; Wed, 29 Aug 2018 00:03:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gVnMBXKc4i1JKgy6ffbRwQOZ0ThpKQAJZ1YKfPm++hw=; b=ZgS7aX3Gd161MtYIFxe4+J6bndokBsbo5aXCfXNj3pxipKi+TVYcErEWiGn27HJGHL UWVYIe2mMiv4As65G44FqFrne5ummVTBxIV0F+IQ0LUUVXUVOi6kTX0Bpo8aLatbXUaY f526m9PouwRhPGgltyy115t1Q9tRqkrsiwdBg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gVnMBXKc4i1JKgy6ffbRwQOZ0ThpKQAJZ1YKfPm++hw=; b=GBp2yYC3/JAlJLzo4JiLPI3jKi72BTetCrzDSAwlMVXZCldwpBDTS9EIB6PZVb1qw/ L32VbbWdYIUqJ+/sHV4RxZjhd3yHHw6URAYEEEvl6gWpYK9DhIeYeCABXHZrrpsjIiSo olU8G8josTreLXrSih38G2mD968fbKwfI4pLLet2/30sUxrgM8LHUXHknCjN/uubbneu AItThwx+wG1H9F50m3h6TsyjHmn6AOZkdJUsGPjBdcq9t4DjE6aVHEsMxqc7xgUDV0m/ 0KarsPecuHMvBZMpwq55SwpKidYFd/fEP6vx8YYnemDC01KON2asKpW1dvfWIUNCVk6W 0gdw== X-Gm-Message-State: APzg51Atbx+SK/rMTxMeuvT9Ci5w4WYdH1zyN+doLh/7WkoG4kiZxlrR jUDzRGF2k5AVzoMjod+0FZLAIg== X-Received: by 2002:a17:902:850c:: with SMTP id bj12-v6mr4823484plb.330.1535526216022; Wed, 29 Aug 2018 00:03:36 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:35 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 5/9] mmc: sdhci: Add 32-bit block count support for v4 mode Date: Wed, 29 Aug 2018 15:03:00 +0800 Message-Id: <1535526184-32718-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Since using 32-bit Block Count would cause problems for auto-cmd23, it can be chosen via host->quirk2. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 14 +++++++++++++- drivers/mmc/host/sdhci.h | 8 ++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 17345b6..604bf4c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1073,7 +1073,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + /* + * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count + * can be supported, in that case 16-bit block count register must be 0. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode && + (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); + } else { + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + } } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c5cc513..f7a1079 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) @@ -462,6 +463,13 @@ struct sdhci_host { * obtainable timeout. */ #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) +/* + * 32-bit block count may not support eMMC where upper bits of CMD23 are used + * for other purposes. Consequently we support 16-bit block count by default. + * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit + * block count. + */ +#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */