From patchwork Thu Aug 30 16:15:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 145550 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp92324ljw; Thu, 30 Aug 2018 09:16:40 -0700 (PDT) X-Google-Smtp-Source: ANB0Vda4Cr0Rve324vL8tAw6xJffAS/KNeETTUA+vcH9QnvVoKXa3NAUbc9YCpIuYKwsPQR9fNk4 X-Received: by 2002:a17:902:48c8:: with SMTP id u8-v6mr11096847plh.152.1535645800403; Thu, 30 Aug 2018 09:16:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535645800; cv=none; d=google.com; s=arc-20160816; b=seDNRjwFKa3b8hJGqI7/xwks64hO+CTEfGbdu6KeGFH9F5edp52r1cGlu+ivDekrzY tbP04hNvlPS+ZaGX3jgcP6+wPXkv6PIhBugn5ddaOWvLqdWqtDqRnH49xaBWPEiuEljn JxmxZSJ4xqYQSavwt79RX2JZ3urHG56ETwR+zVvYOoc9sHgdTsMyjv5ecwKN9AD4X5H1 xum8OUbiXk56fpdm2KXyTryxGdfmNsgwc1L04Ta770M7hsMowVwS9PhYJlWt7rPzFjrn sF/y9uxhniVK1ecjVktbO4yBJx2bIU6X7alEZqwgI8KRkbapyMpp2k0ZxujRwNjVmE8C xgbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=RozllPryD3GkPRtMWEWjoDAYyDfgAVoUGTzvkBtaSfE=; b=zGM08GmgZ3k9SUiTOLwkiQEVi3zAcrFSONGE8GmE7/qdA2OvzVdd7ebRKOtv2An7vY mn7TXXZLKm2S2BTIHdPax90jWAEwH+P46QszICM6lT32D9XqqgcmVIw6vB2xeSd62AcM K/rSSTrol9GZWxTl91BvxJ82mXgOUUuz+OnvF9YR9T9MZSN9XLAN6VRwfrfWoyN7Xuv6 ZNG7U0gLr2hK7H/t617CEcuEz+xC9WrBei/H7wjpZkHUL2zK/siD4FtpYDrWyTS8vbjs ulvmPBwcDyJUvxWj59cwZZZ+zQbptf9f5RI+jiGYwTnmTONCjImBslHktlTTaPRzU3Rn RUIw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 22-v6si7124203pfl.220.2018.08.30.09.16.40; Thu, 30 Aug 2018 09:16:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727577AbeH3USm (ORCPT + 32 others); Thu, 30 Aug 2018 16:18:42 -0400 Received: from foss.arm.com ([217.140.101.70]:44798 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726122AbeH3USl (ORCPT ); Thu, 30 Aug 2018 16:18:41 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1F33F15BF; Thu, 30 Aug 2018 09:15:49 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E4FB53F802; Thu, 30 Aug 2018 09:15:48 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 29EF21AE3630; Thu, 30 Aug 2018 17:16:01 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, benh@au1.ibm.com, torvalds@linux-foundation.org, npiggin@gmail.com, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, Will Deacon Subject: [PATCH 02/12] arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable() Date: Thu, 30 Aug 2018 17:15:36 +0100 Message-Id: <1535645747-9823-3-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1535645747-9823-1-git-send-email-will.deacon@arm.com> References: <1535645747-9823-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org __flush_tlb_[kernel_]pgtable() rely on set_pXd() having a DSB after writing the new table entry and therefore avoid the barrier prior to the TLBI instruction. In preparation for delaying our walk-cache invalidation on the unmap() path, move the DSB into the TLB invalidation routines. Signed-off-by: Will Deacon --- arch/arm64/include/asm/tlbflush.h | 2 ++ 1 file changed, 2 insertions(+) -- 2.1.4 diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 7e2a35424ca4..e257f8655b84 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -213,6 +213,7 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, { unsigned long addr = __TLBI_VADDR(uaddr, ASID(mm)); + dsb(ishst); __tlbi(vae1is, addr); __tlbi_user(vae1is, addr); dsb(ish); @@ -222,6 +223,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) { unsigned long addr = __TLBI_VADDR(kaddr, 0); + dsb(ishst); __tlbi(vaae1is, addr); dsb(ish); }