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[77.136.216.30]) by smtp.gmail.com with ESMTPSA id f187-v6sm970452wmg.17.2018.09.27.07.22.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 27 Sep 2018 07:22:59 -0700 (PDT) From: Daniel Lezcano To: dinguyen@kernel.org Cc: tglx@linutronix.de, marex@denx.de, linux-kernel@vger.kernel.org (open list:CLOCKSOURCE, CLOCKEVENT DRIVERS) Subject: [PATCH] clocksource/drivers/dw_apb: Add reset control Date: Thu, 27 Sep 2018 16:22:51 +0200 Message-Id: <1538058172-6703-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <0873e89e-ea01-e8b6-ade8-01a24bf93cc8@linaro.org> References: <0873e89e-ea01-e8b6-ade8-01a24bf93cc8@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dinh Nguyen Add code to retrieve the reset property from the dw-apb timers and if the property is available, the safe operation is to assert the timer into reset, and followed by a deassert of the timer reset (brings the timer out of reset). This patch is needed for systems where the bootloader has left the timer not used in reset. - Trivial conflict with commit a74bd1ad7a: "Convert to using %pOFn instead of device_node.name" Signed-off-by: Marek Vasut Signed-off-by: Dinh Nguyen Signed-off-by: Daniel Lezcano --- drivers/clocksource/dw_apb_timer_of.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c index fabaa29..db410ac 100644 --- a/drivers/clocksource/dw_apb_timer_of.c +++ b/drivers/clocksource/dw_apb_timer_of.c @@ -22,6 +22,7 @@ #include #include #include +#include #include static void __init timer_get_base_and_rate(struct device_node *np, @@ -29,6 +30,7 @@ static void __init timer_get_base_and_rate(struct device_node *np, { struct clk *timer_clk; struct clk *pclk; + struct reset_control *rstc; *base = of_iomap(np, 0); @@ -36,6 +38,16 @@ static void __init timer_get_base_and_rate(struct device_node *np, panic("Unable to map regs for %pOFn", np); /* + * Reset the timer if the reset control is available, wiping + * out the state the firmware may have left it + */ + rstc = of_reset_control_get(np, NULL); + if (!IS_ERR(rstc)) { + reset_control_assert(rstc); + reset_control_deassert(rstc); + } + + /* * Not all implementations use a periphal clock, so don't panic * if it's not present */