From patchwork Wed Oct 3 11:36:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 148048 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp6349752lji; Wed, 3 Oct 2018 04:37:24 -0700 (PDT) X-Google-Smtp-Source: ACcGV62yp8hKgPexrnzszMSCwfS1mKoVW07P90THMxKBLaLBnKE2KnwK4Wk1QOEWetgtTJuDs3HO X-Received: by 2002:a63:9c01:: with SMTP id f1-v6mr1001147pge.156.1538566644668; Wed, 03 Oct 2018 04:37:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538566644; cv=none; d=google.com; s=arc-20160816; b=UcNBS8n35Nv/MHfZK0bv8mrSgDBTaxvFOkbOAVcGmYYQMXIzJPMLDkVSVE4s38DAxQ 8FhY+dm39coCjvEPaL24KX2VY9cPXlhdZZRjOATrF+DE8N6Zi3UHiYHfQ/pw7noWYLxp XIh9ZOtwW+qR5cKFU72Uumi1NdTDgk8Bv60yGOYTwu12XvuMtr2LWuOkRgp8awfg0bGD j8Fr70QutdGDxVar5mmiQPWbXdOkdTvd1PfMmKddeY/mY3wi7kKjWxjOPEFd2FUpuUxL 5hlfiYool+lhDXMw+vI4JesRCacLolMufy7Oa9EAYGHGFyfZsvGwdCHosUQgzN3MGT/f udVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter; bh=RjHmEivsPVKnzPq6lcVwiYyNrUvc9S3vSUp+3Yy3BOc=; b=K/8adM3jqwQIKr+vKmtKW0uTgM0tpn0Df88ceDn+CjLQr61ESeXxfPazN/DRxtp2Bh jUwhu98UJ8c/bVd7bB59lv91uhYyhgqwYQjDgWKBEa3nhp3mcGuW49t5dUnIY1OfEATc fveY6wqzd0n0ZGLlAHcUSdJiPGcZuoL5Aew63HHa5zTYNDMqF+gzYYajZ66fhJBEB3zV OjkfCFqtuMz64wVlxJRukdgDbxaBw5Uqtemlcb3cSSo0jTMtmyT6v99GGWnYcGIVptkt s3eA5iE3x+PcuezMa2P+1o3T3a4BpSdVcrRALUPnqPLKNFGplF0tkndl0xbGIBR9jQvo Ko/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=Z0d7JSRo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p17-v6si1095819pgj.416.2018.10.03.04.37.24; Wed, 03 Oct 2018 04:37:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=Z0d7JSRo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727432AbeJCSZX (ORCPT + 32 others); Wed, 3 Oct 2018 14:25:23 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:27413 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726617AbeJCSZW (ORCPT ); Wed, 3 Oct 2018 14:25:22 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id w93BaXuS004652; Wed, 3 Oct 2018 20:36:36 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com w93BaXuS004652 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1538566596; bh=RjHmEivsPVKnzPq6lcVwiYyNrUvc9S3vSUp+3Yy3BOc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z0d7JSRoj1kLbCZ3/+HZdOTmqPp1EyMZV6/DFUb8Ca8x/TGOHX8mjz4Vo6FwgNzRe BOdzqErmz7sYbrv9PGjkq4TdyrsMYU3jDGg0nbRfZLeAsdtNxagRwRFf4oC2cQ0MVg bUtr+5Nr4EFNDZ8/Dj/ME6t0+LXBaX8oVQ9JCK0haJF6KExjFy3ntCVOvEwP4GFhyd qrIS3QjFy7USQIc24aeADd1IMoDdVRPmjRgVrlUA+26IioPOrVZmS5onLpu9V8JjTQ MvqC0EZWIhfV0DRbca/vh8Ep1loBIf8YmwsunyYj0yT3nLfiOyuPEGN5kOOtcaYOxP zxm/lvd7WcOSA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: Wolfram Sang , linux-mmc@vger.kernel.org Cc: Ulf Hansson , linux-renesas-soc@vger.kernel.org, Masahiro Yamada , Lee Jones , linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] mmc: tmio: remove TMIO_MMC_HAVE_HIGH_REG flag Date: Wed, 3 Oct 2018 20:36:27 +0900 Message-Id: <1538566587-29452-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538566587-29452-1-git-send-email-yamada.masahiro@socionext.com> References: <1538566587-29452-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TMIO_MMC_HAVE_HIGH_REG is confusing due to its counter-intuitive name. All the TMIO MMC variants (TMIO MMC, Renesas SDHI, UniPhier SD) actually have high registers. It is just that each of them implements its own registers there. The original IP from Panasonic only defines registers 0x00-0xff in the bus_shift=1 review. The register area above them is platform-dependent. In fact, TMIO_MMC_HAVE_HIGH_REG is set only by tmio-mmc.c and used to test the accessibility of CTL_SDIO_REGS. Because it is specific to the TMIO MFD variant, the right thing to do is to move such registers to tmio_mmc.c and delete the TMIO_MMC_HAVE_HIGH_REG flag. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mmc/host/tmio_mmc.c | 7 +++++-- drivers/mmc/host/tmio_mmc.h | 3 --- include/linux/mfd/tmio.h | 7 ------- 3 files changed, 5 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c index 00d291c..4e91020 100644 --- a/drivers/mmc/host/tmio_mmc.c +++ b/drivers/mmc/host/tmio_mmc.c @@ -24,6 +24,11 @@ #include "tmio_mmc.h" +/* Registers specific to this variant */ +#define CTL_SDIO_REGS 0x100 +#define CTL_CLK_AND_WAIT_CTL 0x138 +#define CTL_RESET_SDIO 0x1e0 + static void tmio_mmc_clk_start(struct tmio_mmc_host *host) { sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | @@ -161,8 +166,6 @@ static int tmio_mmc_probe(struct platform_device *pdev) goto cell_disable; } - pdata->flags |= TMIO_MMC_HAVE_HIGH_REG; - host = tmio_mmc_host_alloc(pdev, pdata); if (IS_ERR(host)) { ret = PTR_ERR(host); diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h index a1a661b..18b4308 100644 --- a/drivers/mmc/host/tmio_mmc.h +++ b/drivers/mmc/host/tmio_mmc.h @@ -47,9 +47,6 @@ #define CTL_RESET_SD 0xe0 #define CTL_VERSION 0xe2 #define CTL_SDIF_MODE 0xe6 -#define CTL_SDIO_REGS 0x100 -#define CTL_CLK_AND_WAIT_CTL 0x138 -#define CTL_RESET_SDIO 0x1e0 /* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */ #define TMIO_STOP_STP BIT(0) diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h index 7786621..1e70060 100644 --- a/include/linux/mfd/tmio.h +++ b/include/linux/mfd/tmio.h @@ -62,13 +62,6 @@ #define TMIO_MMC_USE_GPIO_CD BIT(5) /* - * Some controllers doesn't have over 0x100 register. - * it is used to checking accessibility of - * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL - */ -#define TMIO_MMC_HAVE_HIGH_REG BIT(6) - -/* * Some controllers have CMD12 automatically * issue/non-issue register */