From patchwork Wed May 22 10:35:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 164790 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp694161ili; Wed, 22 May 2019 03:36:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqyDxIcWP1O5T6o2z+hrqYXhJ712BPpH1OdQK3VIBwpRgJo/tnp4yCwzp2O6wr0jl0vzr4uf X-Received: by 2002:a63:c64c:: with SMTP id x12mr88434969pgg.379.1558521363727; Wed, 22 May 2019 03:36:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558521363; cv=none; d=google.com; s=arc-20160816; b=nhPSm4yn5VwKpA+b7h3Z1N2PR4j5dK8vaVEa6FTpVFK0KttTcF2VuQ+DQR2ndkCoPT FFB/6yNJMdH63Fiy0A7XvVo3H6cakNJJl6zodXemWjeUz+JbV1hx/tRD0pJFmuGxaNQr 21YzkrD7vWwBzw+HyKs4BYUOOB8tlijrTCjzQKkiJwoycnzgBDG0NG6FO6aCVEYxfre7 MHBRIcaNkJB+2cdvuP8Fb+ZzksLhEeRkSA5dFNZKObgnLydetMcAc6W/vYgig0GKt673 yZX/z2R+bXCt8UshZhQbm7VPGmN85nlty23JGSRgQu4R55GPni0J8LX4KLvMaVwP6cgz tu5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=VYrdyVdXitr0IukJNDx1qYS4TusT1Vc6l7Tt7/OvRJU=; b=v0dWFBLMVQxIBbfhkBcPM8UVM1ycedTH1TWq6efc7PGRIcYvUR487pcwacRg1o7sQT i5YbHZssqESJMavGDkeGXPtta+Wu9GjHs9D+QBksdwW4Cu8HkxazUjZX7IFG0MzLa1sm luOmvVJ1+kqx2F55j16aucW9xSHAZQjZv1a09UNGaFhlnOh36JIJRIx9hYQHZsFA2ilD x65ExMFxpkJBnmCT0cOvORVYXN4Ewvqak7lZ0+kDuANBMiTnIenUFw4ImwmTn3IWThBt 49fGQUXRKj8VKczE6wo2bCxiYCDVOzMIIk2zsK4RF51nLnEfiTov7VwI5mfKz1uJD7ol e+qw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h68si25312309pgc.270.2019.05.22.03.36.03; Wed, 22 May 2019 03:36:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729513AbfEVKgC (ORCPT + 30 others); Wed, 22 May 2019 06:36:02 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:47256 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729499AbfEVKgA (ORCPT ); Wed, 22 May 2019 06:36:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5FD651993; Wed, 22 May 2019 03:35:59 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.196.93]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 502003F575; Wed, 22 May 2019 03:35:58 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org, coresight@lists.linaro.org, Suzuki K Poulose Subject: [TEST PATCH 31/30][EDK2] edk2-platform: juno: Update ACPI CoreSight Bindings Date: Wed, 22 May 2019 11:35:04 +0100 Message-Id: <1558521304-27469-32-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558521304-27469-1-git-send-email-suzuki.poulose@arm.com> References: <1558521304-27469-1-git-send-email-suzuki.poulose@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ACPI bindings for CoreSight components on the Juno-r0 board. Please note that the bindings apply only for the juno-r0. The layout on r1 and r2 are slightly different and will need dynamic ACPI table support to be able to use a single UEFI image. Signed-off-by: Suzuki K Poulose --- Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl | 241 +++++++++++++++++++++++++++++++ 1 file changed, 241 insertions(+) -- 2.7.4 diff --git a/Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl b/Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl index 702b057..c70e8ac 100644 --- a/Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl +++ b/Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl @@ -14,6 +14,51 @@ #include "ArmPlatform.h" +#define ACPI_GRAPH_REV 0 +#define ACPI_GRAPH_UUID "ab02a46b-74c7-45a2-bd68-f7d344ef2153" + +#define CORESIGHT_GRAPH_UUID "3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd" + +#define CS_LINK_MASTER 1 +#define CS_LINK_SLAVE 0 + + +#define DSD_CS_GRAPH_BEGIN(_nports) \ + Package () { \ + 1, // GraphID \ + ToUUID(CORESIGHT_GRAPH_UUID), \ + _nports, + +#define DSD_CS_GRAPH_END \ + } + +#define DSD_GRAPH_BEGIN(_nports) \ + ToUUID(ACPI_GRAPH_UUID), \ + Package() { \ + ACPI_GRAPH_REV, \ + 1, \ + DSD_CS_GRAPH_BEGIN(_nports) + +#define DSD_GRAPH_END \ + DSD_CS_GRAPH_END \ + } + +#define DSD_PORTS_BEGIN(_nports) \ + Name (_DSD, Package () { \ + DSD_GRAPH_BEGIN(_nports) + +#define DSD_PORTS_END \ + DSD_GRAPH_END \ + }) + +#define CS_PORT(_port, _rport, _rphandle, _dir) \ + Package () { _port, _rport, _rphandle, _dir} + +#define CS_INPUT_PORT(_port, _rport, _rphandle) \ + CS_PORT(_port, _rport, _rphandle, CS_LINK_SLAVE) +#define CS_OUTPUT_PORT(_port, _rport, _rphandle) \ + CS_PORT(_port, _rport, _rphandle, CS_LINK_MASTER) + DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) { Scope(_SB) { // @@ -122,15 +167,56 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O Method (_LPI, 0, NotSerialized) { return(PLPI) } + + Device(ETM0) { // ETM on Cluster0 CPU0 + Name (_HID, "ARMHC500") + Name (_CID, "ARMHC500") + Name (_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x22040000, 0x1000) + }) + + DSD_PORTS_BEGIN(1) + CS_OUTPUT_PORT(0, 0, \_SB_.CLU0.FUN0) + DSD_PORTS_END + + } // ETM0 } + Device(CPU1) { // A57-1: Cluster 0, Cpu 1 Name(_HID, "ACPI0007") Name(_UID, 5) Method (_LPI, 0, NotSerialized) { return(PLPI) } + Device(ETM1) { // ETM on Cluster0 CPU1 + Name (_HID, "ARMHC500") + Name (_CID, "ARMHC500") + Name (_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x22140000, 0x1000) + }) + + DSD_PORTS_BEGIN(1) + CS_OUTPUT_PORT(0, 1, \_SB_.CLU0.FUN0) + DSD_PORTS_END + + } // ETM1 } + + Device(FUN0) { + Name(_HID, "ARMHC9FF") + Name(_CID, "ARMHC9FF") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x220c0000, 0x1000) + }) + + DSD_PORTS_BEGIN(3) + CS_OUTPUT_PORT(0, 0, \_SB_.MFUN), + CS_INPUT_PORT(0, 0, \_SB_.CLU0.CPU0.ETM0), + CS_INPUT_PORT(1, 0, \_SB_.CLU0.CPU1.ETM1) + DSD_PORTS_END + } // CL0.FUN0 } + Device (CLU1) { // Cluster1 state Name(_HID, "ACPI0010") Name(_UID, 2) @@ -208,19 +294,45 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O "CorePwrDn" }, }) + Device(CPU2) { // A53-0: Cluster 1, Cpu 0 Name(_HID, "ACPI0007") Name(_UID, 0) Method (_LPI, 0, NotSerialized) { return(PLPI) } + Device(ETM2) { // ETM on Cluster1, CPU0 + Name (_HID, "ARMHC500") + Name (_CID, "ARMHC500") + Name (_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x23040000, 0x1000) + }) + + DSD_PORTS_BEGIN(1) + CS_OUTPUT_PORT(0, 0, \_SB_.CLU1.FUN1) + DSD_PORTS_END + + } // ETM2 } + Device(CPU3) { // A53-1: Cluster 1, Cpu 1 Name(_HID, "ACPI0007") Name(_UID, 1) Method (_LPI, 0, NotSerialized) { return(PLPI) } + Device(ETM3) { // ETM on Cluster1, CPU1 + Name (_HID, "ARMHC500") + Name (_CID, "ARMHC500") + Name (_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x23140000, 0x1000) + }) + + DSD_PORTS_BEGIN(1) + CS_OUTPUT_PORT(0, 1, \_SB_.CLU1.FUN1) + DSD_PORTS_END + + } // ETM3 } Device(CPU4) { // A53-2: Cluster 1, Cpu 2 Name(_HID, "ACPI0007") @@ -228,6 +340,18 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O Method (_LPI, 0, NotSerialized) { return(PLPI) } + Device(ETM4) { // ETM on Cluster1, CPU2 + Name (_HID, "ARMHC500") // ETM + Name (_CID, "ARMHC500") // ETM + Name (_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x23240000, 0x1000) + }) + + DSD_PORTS_BEGIN(1) + CS_OUTPUT_PORT(0, 2, \_SB_.CLU1.FUN1) + DSD_PORTS_END + + } // ETM4 } Device(CPU5) { // A53-3: Cluster 1, Cpu 3 Name(_HID, "ACPI0007") @@ -235,9 +359,126 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O Method (_LPI, 0, NotSerialized) { return(PLPI) } + Device(ETM5) { // ETM on Cluster1, CPU3 + Name (_HID, "ARMHC500") // ETM + Name (_CID, "ARMHC500") // ETM + Name (_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x23340000, 0x1000) + }) + + DSD_PORTS_BEGIN(1) + CS_OUTPUT_PORT(0, 3, \_SB_.CLU1.FUN1) + DSD_PORTS_END + } // ETM5 } + Device(FUN1) { + Name(_HID, "ARMHC9FF") + Name(_CID, "ARMHC9FF") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x230c0000, 0x1000) + }) + + DSD_PORTS_BEGIN(5) + CS_OUTPUT_PORT(0, 1, \_SB_.MFUN), + CS_INPUT_PORT(0, 0, \_SB_.CLU1.CPU2.ETM2), + CS_INPUT_PORT(1, 0, \_SB_.CLU1.CPU3.ETM3), + CS_INPUT_PORT(2, 0, \_SB_.CLU1.CPU4.ETM4), + CS_INPUT_PORT(3, 0, \_SB_.CLU1.CPU5.ETM5) + DSD_PORTS_END + } // CL1.FUN1 } + Device(STM0) { + Name(_HID, "ARMHC502") // STM + Name(_CID, "ARMHC502") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x20100000, 0x1000) + Memory32Fixed(ReadWrite, 0x28000000, 0x1000000) + }) + DSD_PORTS_BEGIN(1) + CS_OUTPUT_PORT(0, 2, \_SB_.MFUN) + DSD_PORTS_END + } + + Device(MFUN) { + Name(_HID, "ARMHC9FF") // Funnel + Name(_CID, "ARMHC9FF") // Funnel + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x20040000, 0x1000) + }) + + DSD_PORTS_BEGIN(4) + CS_OUTPUT_PORT(0, 0, \_SB_.ETF0), + CS_INPUT_PORT(0, 0, \_SB_.CLU0.FUN0), + CS_INPUT_PORT(1, 0, \_SB_.CLU1.FUN1), + CS_INPUT_PORT(2, 0, \_SB_.STM0) + DSD_PORTS_END + + } // MFUN-nel + + Device(ETF0) { + Name(_HID, "ARMHC97C") // TMC + Name(_CID, "ARMHC97C") // TMC + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x20010000, 0x1000) + }) + + DSD_PORTS_BEGIN(2) + CS_OUTPUT_PORT(0, 1, \_SB_.RPL), + CS_INPUT_PORT(0, 0, \_SB_.MFUN) + DSD_PORTS_END + + } // ETF0 + + Device(RPL) { + Name(_HID, "ARMHC98D") // Replicator + Name(_CID, "ARMHC98D") // Replicator + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x20120000, 0x1000) + }) + + DSD_PORTS_BEGIN(3) + CS_OUTPUT_PORT(0, 0, \_SB_.TPIU), + CS_OUTPUT_PORT(1, 0, \_SB_.ETR), + CS_INPUT_PORT(0, 0, \_SB_.ETF0) + DSD_PORTS_END + + } // RPL + + Device(ETR) { + Name(_HID, "ARMHC97C") // TMC + Name(_CID, "ARMHC97C") // TMC + Name(_CCA, 0) // The ETR on this platform is not coherent + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x20070000, 0x1000) + }) + + Name(_DSD, Package() { + DSD_GRAPH_BEGIN(1) + CS_INPUT_PORT(0, 1, \_SB_.RPL) + DSD_GRAPH_END, + + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package(2) {"arm,scatter-gather", 1} + } + }) + + } // ETR + + Device(TPIU) { + Name(_HID, "ARMHC979") // TPIU + Name(_CID, "ARMHC979") // TPIU + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x20030000, 0x1000) + }) + + DSD_PORTS_BEGIN(1) + CS_INPUT_PORT(0, 0, \_SB_.RPL) + DSD_PORTS_END + + } // TPIU + // // Keyboard and Mouse //