From patchwork Wed May 29 09:58:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 165365 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9655628ili; Wed, 29 May 2019 03:00:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqwKtwxqw1KPI8JMPUX2lRpqH/cJZ0I11HOCAfBvG7JXAgVQo7cChg6Lk6+UtIatk9ObiQno X-Received: by 2002:a17:902:b195:: with SMTP id s21mr38639258plr.16.1559124029848; Wed, 29 May 2019 03:00:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559124029; cv=none; d=google.com; s=arc-20160816; b=RScJqSKiH1h6Ix3yFdrvXVy/tUu8e0sFvGLh+Br/hUvl2XwcYh1dnYdr+GkMsw8UPE jo0ksq07pQYsC2Birm0ZAApXc0C1zBB7DEvRmLQGO+KfL49Ikry9SoVqbmhpVwm1u4eE IQVmP06DB1ymlmaisKQHz3YNmBFduUUt9+6FFQUxdTvmWrHQ3ohUWKoKz6tV4M4xr0h0 imnciGBE9oao29PDUaUYytZMHfuEdhTbjh1vWyIwAY1bSy5BTj+ruVrjuEvmvdRiN9J/ D7Y2GwfXjlOZiJLXwk1T6bs0WTfdH71ikSTVk1p6uNNGo+/RCgwGWXIl3+NELNhCX2uj azBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=NB6XmEn6QSnY61VDD0E3BWi7e1Femfj1E0/RYFH2vP0=; b=yfBGNlYGJHI3koiXz+wkVGGMfM379wZ8IuoeXeNcyDMMrAeNfDGsRkua6SqjUjytN3 UzgyO9eUHBib8MkHiCgSXMHZvu27nAt5DUoVhizJwZrNyLqTzSfL0isFu/IgfDJDsury /uwT5JE0EVVDrLkQ9l8/1FMOHlaihNG34HNa4XkU8BIMRD5D1xf1+YG/xs53NXwo5eOU YwfdRYOi6oLeB/WDFCbl63lfif1B0dbvzFBNMvwNAYCMy8KjiINKbw8InovWPQA8HRoC BYA4Z5X5mZsVqFEE6eZQHB+YEPeQ8mDrDEnZoGhdO86uzzHRKycGoWI8VFkeZnEO6rxj 1IOQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d23si24713060pgv.513.2019.05.29.03.00.29; Wed, 29 May 2019 03:00:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726816AbfE2KA2 (ORCPT + 30 others); Wed, 29 May 2019 06:00:28 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:35664 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726658AbfE2KAZ (ORCPT ); Wed, 29 May 2019 06:00:25 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 9D5EF2381E56D4F64836; Wed, 29 May 2019 18:00:22 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Wed, 29 May 2019 18:00:12 +0800 From: John Garry To: , CC: , , , Luo Jiaxing , John Garry Subject: [PATCH 5/6] scsi: hisi_sas: Ignore the error code between phy down to phy up Date: Wed, 29 May 2019 17:58:46 +0800 Message-ID: <1559123927-160502-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1559123927-160502-1-git-send-email-john.garry@huawei.com> References: <1559123927-160502-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Luo Jiaxing Several error code will be generated between PHY down to up. This issue was introduced by HW design, so the designers come to a conclusion that we should ignore these several error code. Signed-off-by: Jiaxing Luo Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.17.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 492ada65d41a..fbf0a1e9c8c2 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -911,8 +911,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); + static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | + BIT(CHL_INT2_RX_CODE_ERR_OFF) | + BIT(CHL_INT2_RX_INVLD_DW_OFF); u32 state; + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk); + cfg &= ~PHY_CFG_ENA_MSK; hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); @@ -923,6 +929,15 @@ static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) cfg |= PHY_CFG_PHY_RST_MSK; hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); } + + udelay(1); + + hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); + hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); + hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); + + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk); + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk); } static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)