| Message ID | 1570733080-21015-5-git-send-email-Dave.Martin@arm.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: ARMv8.5-A: Branch Target Identification support | expand |
Dave Martin <Dave.Martin@arm.com> writes: > Commit d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise > to userspace") exposes ID_AA64PFR1_EL1 to userspace, but didn't > update the documentation to match. > > Add it. > > Signed-off-by: Dave Martin <Dave.Martin@arm.com> > > --- > > Note to maintainers: > > * This patch has been racing with various other attempts to fix > the same documentation in the meantime. > > Since this patch only fixes the documenting for pre-existing > features, it can safely be dropped if appropriate. > > The _new_ documentation relating to BTI feature reporting > is in a subsequent patch, and needs to be retained. > --- > Documentation/arm64/cpu-feature-registers.rst | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst > index 2955287..b86828f 100644 > --- a/Documentation/arm64/cpu-feature-registers.rst > +++ b/Documentation/arm64/cpu-feature-registers.rst > @@ -168,8 +168,15 @@ infrastructure: > +------------------------------+---------+---------+ > > > - 3) MIDR_EL1 - Main ID Register > + 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 > + +------------------------------+---------+---------+ > + | Name | bits | visible | > + +------------------------------+---------+---------+ > + | SSBS | [7-4] | y | > + +------------------------------+---------+---------+ > + > > + 4) MIDR_EL1 - Main ID Register > +------------------------------+---------+---------+ > | Name | bits | visible | > +------------------------------+---------+---------+ > @@ -188,7 +195,7 @@ infrastructure: > as available on the CPU where it is fetched and is not a system > wide safe value. > > - 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > + 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 If I'm not mistaken .rst has support for auto-enumeration if the # character is used. That might reduce the pain of re-numbering in future. > > +------------------------------+---------+---------+ > | Name | bits | visible | > @@ -210,7 +217,7 @@ infrastructure: > | DPB | [3-0] | y | > +------------------------------+---------+---------+ > > - 5) ID_AA64MMFR2_EL1 - Memory model feature register 2 > + 6) ID_AA64MMFR2_EL1 - Memory model feature register 2 > > +------------------------------+---------+---------+ > | Name | bits | visible | > @@ -218,7 +225,7 @@ infrastructure: > | AT | [35-32] | y | > +------------------------------+---------+---------+ > > - 6) ID_AA64ZFR0_EL1 - SVE feature ID register 0 > + 7) ID_AA64ZFR0_EL1 - SVE feature ID register 0 > > +------------------------------+---------+---------+ > | Name | bits | visible | -- Alex Bennée
On Fri, Oct 11, 2019 at 02:19:48PM +0100, Alex Bennée wrote: > > Dave Martin <Dave.Martin@arm.com> writes: > > > Commit d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise > > to userspace") exposes ID_AA64PFR1_EL1 to userspace, but didn't > > update the documentation to match. > > > > Add it. > > > > Signed-off-by: Dave Martin <Dave.Martin@arm.com> > > > > --- > > > > Note to maintainers: > > > > * This patch has been racing with various other attempts to fix > > the same documentation in the meantime. > > > > Since this patch only fixes the documenting for pre-existing > > features, it can safely be dropped if appropriate. > > > > The _new_ documentation relating to BTI feature reporting > > is in a subsequent patch, and needs to be retained. > > --- > > Documentation/arm64/cpu-feature-registers.rst | 15 +++++++++++---- > > 1 file changed, 11 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst > > index 2955287..b86828f 100644 > > --- a/Documentation/arm64/cpu-feature-registers.rst > > +++ b/Documentation/arm64/cpu-feature-registers.rst > > @@ -168,8 +168,15 @@ infrastructure: > > +------------------------------+---------+---------+ > > > > > > - 3) MIDR_EL1 - Main ID Register > > + 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 > > + +------------------------------+---------+---------+ > > + | Name | bits | visible | > > + +------------------------------+---------+---------+ > > + | SSBS | [7-4] | y | > > + +------------------------------+---------+---------+ > > + > > > > + 4) MIDR_EL1 - Main ID Register > > +------------------------------+---------+---------+ > > | Name | bits | visible | > > +------------------------------+---------+---------+ > > @@ -188,7 +195,7 @@ infrastructure: > > as available on the CPU where it is fetched and is not a system > > wide safe value. > > > > - 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > > + 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > > If I'm not mistaken .rst has support for auto-enumeration if the # > character is used. That might reduce the pain of re-numbering in future. Ack, though it would be good to go one better and generate this document from the cpufeature.c tables (or from some common source). The numbers are relatively easy to maintain -- remembering to update the document at all seems the bigger maintenance headache right now. I think this particular patch is superseded by similar fixes from other people, just not in torvalds/master yet. [...] Cheers ---Dave
On Fri, Oct 11, 2019 at 03:51:49PM +0100, Dave Martin wrote: > On Fri, Oct 11, 2019 at 02:19:48PM +0100, Alex Bennée wrote: > > > - 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > > > + 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > > If I'm not mistaken .rst has support for auto-enumeration if the # > > character is used. That might reduce the pain of re-numbering in future. > Ack, though it would be good to go one better and generate this document > from the cpufeature.c tables (or from some common source). The numbers > are relatively easy to maintain -- remembering to update the document > at all seems the bigger maintenance headache right now. I agree, it'd be better if the table were autogenerated. Having tried doing the modification to # it does mean that the document looks a bit weird when viewing it as a text file in the kernel source which TBH is how I suspect a lot of people will view it so given the infrequency with which new registers are added I'm not sure it's worth it. > I think this particular patch is superseded by similar fixes from other > people, just not in torvalds/master yet. Nor in -next for the minute :/
On Mon, Oct 21, 2019 at 08:18:18PM +0100, Mark Brown wrote: > On Fri, Oct 11, 2019 at 03:51:49PM +0100, Dave Martin wrote: > > On Fri, Oct 11, 2019 at 02:19:48PM +0100, Alex Bennée wrote: > > > > > - 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > > > > + 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > > > > If I'm not mistaken .rst has support for auto-enumeration if the # > > > character is used. That might reduce the pain of re-numbering in future. > > > Ack, though it would be good to go one better and generate this document > > from the cpufeature.c tables (or from some common source). The numbers > > are relatively easy to maintain -- remembering to update the document > > at all seems the bigger maintenance headache right now. > > I agree, it'd be better if the table were autogenerated. Having tried > doing the modification to # it does mean that the document looks a bit > weird when viewing it as a text file in the kernel source which TBH is > how I suspect a lot of people will view it so given the infrequency with > which new registers are added I'm not sure it's worth it. > > > I think this particular patch is superseded by similar fixes from other > > people, just not in torvalds/master yet. > > Nor in -next for the minute :/ Which patch is missing? The only other one on my radar is "docs/arm64: cpu-feature-registers: Documents missing visible fields" which is currently in -next as a8613e7070e7. "similar fixes from other people" isn't very specific :( Will
diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst index 2955287..b86828f 100644 --- a/Documentation/arm64/cpu-feature-registers.rst +++ b/Documentation/arm64/cpu-feature-registers.rst @@ -168,8 +168,15 @@ infrastructure: +------------------------------+---------+---------+ - 3) MIDR_EL1 - Main ID Register + 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | SSBS | [7-4] | y | + +------------------------------+---------+---------+ + + 4) MIDR_EL1 - Main ID Register +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ @@ -188,7 +195,7 @@ infrastructure: as available on the CPU where it is fetched and is not a system wide safe value. - 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 + 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 +------------------------------+---------+---------+ | Name | bits | visible | @@ -210,7 +217,7 @@ infrastructure: | DPB | [3-0] | y | +------------------------------+---------+---------+ - 5) ID_AA64MMFR2_EL1 - Memory model feature register 2 + 6) ID_AA64MMFR2_EL1 - Memory model feature register 2 +------------------------------+---------+---------+ | Name | bits | visible | @@ -218,7 +225,7 @@ infrastructure: | AT | [35-32] | y | +------------------------------+---------+---------+ - 6) ID_AA64ZFR0_EL1 - SVE feature ID register 0 + 7) ID_AA64ZFR0_EL1 - SVE feature ID register 0 +------------------------------+---------+---------+ | Name | bits | visible |
Commit d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise to userspace") exposes ID_AA64PFR1_EL1 to userspace, but didn't update the documentation to match. Add it. Signed-off-by: Dave Martin <Dave.Martin@arm.com> --- Note to maintainers: * This patch has been racing with various other attempts to fix the same documentation in the meantime. Since this patch only fixes the documenting for pre-existing features, it can safely be dropped if appropriate. The _new_ documentation relating to BTI feature reporting is in a subsequent patch, and needs to be retained. --- Documentation/arm64/cpu-feature-registers.rst | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) -- 2.1.4