From patchwork Mon Jun 20 03:50:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xinliang Liu X-Patchwork-Id: 70401 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp1321055qgy; Sun, 19 Jun 2016 20:52:01 -0700 (PDT) X-Received: by 10.36.84.79 with SMTP id t76mr14190303ita.63.1466394709696; Sun, 19 Jun 2016 20:51:49 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c133si30517130pfc.145.2016.06.19.20.51.49; Sun, 19 Jun 2016 20:51:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752692AbcFTDvP (ORCPT + 30 others); Sun, 19 Jun 2016 23:51:15 -0400 Received: from mail-pf0-f178.google.com ([209.85.192.178]:35503 "EHLO mail-pf0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752565AbcFTDuk (ORCPT ); Sun, 19 Jun 2016 23:50:40 -0400 Received: by mail-pf0-f178.google.com with SMTP id c2so49587145pfa.2 for ; Sun, 19 Jun 2016 20:50:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1aL2gM5Ld6/lYsniqeUel1kk9Wi5DdIgQydQ+QIQvi8=; b=BFpbwgErqaZAsHnf88PueGiBjCMOHcfX1tz2Y1Cn33Lr+dEpoecekrB1AaKrpZ5Fii D5cHQKnE+VC5Ur3pXU9/yiBRSd0YTOq3cY38gYz9R3JTtjUREb71EKwJE8U1Y5Ur6n8q Ui9wVz95Q7gL1O1OFNndLUc9bqqdhKWBImE5I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1aL2gM5Ld6/lYsniqeUel1kk9Wi5DdIgQydQ+QIQvi8=; b=U6n/ism5dHG/zD64ObZlKBFKEI9NmqHS+P7qE6T3deMHJzz8P7iACi7agZ7in+RbyZ U7Kaay1eg1D5FkdXZ08bjaaK2YEEyiNmBMKNOeZ66881QBXVPC50cTDOMmg006+C1v8u KZuwwTeXlC33M6jI2Ql2Yiri7tZi4EwcFX8vuuyrKgI0XANGwWKv9NXrjDzSbCJ3K1fz MsSDor0rpjdsYMdBd3CHzOY1N6QZlupJBs3F9THTmcj3WUGRUsulUYccnnFtvrYoIhx+ 6xMpHepsJIxa+MlVIDr9vZ+rZzkcS8STpwwTeuImuTSvowvM5vMvH7xdiNGsAICMx2iS FNdw== X-Gm-Message-State: ALyK8tKbRa7534sX8WvUtJ3TdxT2/WCWGCimvcSCOqcmq4PQDsn+mAjlUZQtKcqAwkqf88UC X-Received: by 10.98.92.133 with SMTP id q127mr19418964pfb.103.1466394639771; Sun, 19 Jun 2016 20:50:39 -0700 (PDT) Received: from HTSAT-OPENLAB-SERVER.localdomain ([14.154.190.136]) by smtp.gmail.com with ESMTPSA id i187sm50990403pfc.62.2016.06.19.20.50.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 19 Jun 2016 20:50:39 -0700 (PDT) From: Xinliang Liu To: p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org, xuwei5@hisilicon.com, puck.chen@hisilicon.com, saberlily.xia@hisilicon.com, kong.kongxinwei@hisilicon.com, guodong.xu@linaro.org, Xinliang Liu Subject: [PATCH v3 3/4] reset: hisilicon: Change to syscon register access Date: Mon, 20 Jun 2016 11:50:06 +0800 Message-Id: <20160620035007.229629-4-xinliang.liu@linaro.org> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160620035007.229629-1-xinliang.liu@linaro.org> References: <20160620035007.229629-1-xinliang.liu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen Feng There are two reset controllers in hi6220 SoC: The peripheral reset controller bits are part of sysctrl registers. The media reset controller bits are part of mediactrl registers. So change register access to syscon way. And rename current reset controller to peripheral one. Signed-off-by: Chen Feng Signed-off-by: Xia Qing Signed-off-by: Xinliang Liu --- drivers/reset/hisilicon/hi6220_reset.c | 85 ++++++++++++++++++---------------- 1 file changed, 45 insertions(+), 40 deletions(-) -- 2.8.3 diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c index 8f55fd4a2630..686fea9e2c54 100644 --- a/drivers/reset/hisilicon/hi6220_reset.c +++ b/drivers/reset/hisilicon/hi6220_reset.c @@ -1,7 +1,8 @@ /* * Hisilicon Hi6220 reset controller driver * - * Copyright (c) 2015 Hisilicon Limited. + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2015-2016 Hisilicon Limited. * * Author: Feng Chen * @@ -15,81 +16,85 @@ #include #include #include +#include +#include +#include #include #include #include -#define ASSERT_OFFSET 0x300 -#define DEASSERT_OFFSET 0x304 -#define MAX_INDEX 0x509 +#define PERIPH_ASSERT_OFFSET 0x300 +#define PERIPH_DEASSERT_OFFSET 0x304 +#define PERIPH_MAX_INDEX 0x509 #define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev) struct hi6220_reset_data { - void __iomem *assert_base; - void __iomem *deassert_base; - struct reset_controller_dev rc_dev; + struct reset_controller_dev rc_dev; + struct regmap *regmap; }; -static int hi6220_reset_assert(struct reset_controller_dev *rc_dev, - unsigned long idx) +static int hi6220_peripheral_assert(struct reset_controller_dev *rc_dev, + unsigned long idx) { struct hi6220_reset_data *data = to_reset_data(rc_dev); + struct regmap *regmap = data->regmap; + u32 bank = idx >> 8; + u32 offset = idx & 0xff; + u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10; - int bank = idx >> 8; - int offset = idx & 0xff; - - writel(BIT(offset), data->assert_base + (bank * 0x10)); - - return 0; + return regmap_write(regmap, reg, BIT(offset)); } -static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev, - unsigned long idx) +static int hi6220_peripheral_deassert(struct reset_controller_dev *rc_dev, + unsigned long idx) { struct hi6220_reset_data *data = to_reset_data(rc_dev); + struct regmap *regmap = data->regmap; + u32 bank = idx >> 8; + u32 offset = idx & 0xff; + u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10; - int bank = idx >> 8; - int offset = idx & 0xff; - - writel(BIT(offset), data->deassert_base + (bank * 0x10)); - - return 0; + return regmap_write(regmap, reg, BIT(offset)); } -static const struct reset_control_ops hi6220_reset_ops = { - .assert = hi6220_reset_assert, - .deassert = hi6220_reset_deassert, +static const struct reset_control_ops hi6220_peripheral_reset_ops = { + .assert = hi6220_peripheral_assert, + .deassert = hi6220_peripheral_deassert, }; static int hi6220_reset_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; struct hi6220_reset_data *data; - struct resource *res; - void __iomem *src_base; + struct regmap *regmap; - data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - src_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(src_base)) - return PTR_ERR(src_base); + regmap = syscon_node_to_regmap(np); + if (IS_ERR(regmap)) { + dev_err(dev, "failed to get reset controller regmap\n"); + return PTR_ERR(regmap); + } - data->assert_base = src_base + ASSERT_OFFSET; - data->deassert_base = src_base + DEASSERT_OFFSET; - data->rc_dev.nr_resets = MAX_INDEX; - data->rc_dev.ops = &hi6220_reset_ops; - data->rc_dev.of_node = pdev->dev.of_node; + data->regmap = regmap; + data->rc_dev.of_node = np; + data->rc_dev.ops = &hi6220_peripheral_reset_ops; + data->rc_dev.nr_resets = PERIPH_MAX_INDEX; return reset_controller_register(&data->rc_dev); } static const struct of_device_id hi6220_reset_match[] = { - { .compatible = "hisilicon,hi6220-sysctrl" }, - { }, + { + .compatible = "hisilicon,hi6220-sysctrl", + }, + { /* sentinel */ }, }; +MODULE_DEVICE_TABLE(of, hi6220_reset_match); static struct platform_driver hi6220_reset_driver = { .probe = hi6220_reset_probe,