From patchwork Wed Oct 19 13:28:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 78259 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp278809qge; Wed, 19 Oct 2016 07:30:33 -0700 (PDT) X-Received: by 10.99.116.24 with SMTP id p24mr9622456pgc.167.1476887433244; Wed, 19 Oct 2016 07:30:33 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l64si24532972pfa.191.2016.10.19.07.30.32; Wed, 19 Oct 2016 07:30:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S942404AbcJSOaO (ORCPT + 27 others); Wed, 19 Oct 2016 10:30:14 -0400 Received: from mail-lf0-f44.google.com ([209.85.215.44]:35570 "EHLO mail-lf0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932833AbcJSOaL (ORCPT ); Wed, 19 Oct 2016 10:30:11 -0400 Received: by mail-lf0-f44.google.com with SMTP id l131so25652105lfl.2 for ; Wed, 19 Oct 2016 07:30:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tkUmL75NPdliuFdJtsaURvirDlq4rXMfgD/e3pYmlJs=; b=ZaGuElOCGXNZfclX/+6VQTcadLtuUg4E3kXZNlWvn91wYESIABELPVy4eml6vMl49s 1G1k/WWeGepggSu6fM52EKIOfTSHH1jSAyTAFN7ewINjy6ulC65hUgB9aKGKMIro4omG 02fHexB9gpEm6zAY6fioXzU8Pj0YH9JvYchSk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tkUmL75NPdliuFdJtsaURvirDlq4rXMfgD/e3pYmlJs=; b=FqnlrE9SPc5KSu+Kg8iglRvySjQpVd2pxnUqtWwV8EWp7WbQN2LYZx89Xt/4dFxk9A Fr3xd4v6HD+hbqcIx1gairDpQKsCVvZBdJY4Jff6Lh960qSSKDe2YzBLb/Fk0p80cB0z 0GtiGdcKnOfiUOPfKkN2NxfwSwxJjnfKO75/H483wUCSE1S08TJPfpQFdZNyailZwo2s 9f5oDUWv9UTY7F+iWJmpGKHJ5XC3ufrMe2FF+TMT0Y2ehkhb4QSMb/I0SuxLEtNQFOV2 /ONjIktHWxxdMjWTzaWfaaBqX8E6NlvD6BhE8okSN2w7OwiMFrl7oEYuYgcSodnlibQG vMBQ== X-Gm-Message-State: AA6/9RldT/a0jmjfD+NMoc1rTDhGl2vMieqaQMmtF79PBLP25Ewt0qf+ktZK02R8bIp+rFOP X-Received: by 10.25.160.21 with SMTP id j21mr5172758lfe.149.1476883704322; Wed, 19 Oct 2016 06:28:24 -0700 (PDT) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id z204sm3663405lfa.11.2016.10.19.06.28.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 19 Oct 2016 06:28:23 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [RESEND/PATCH v6 3/3] clk: qcom: Add A53 clock driver Date: Wed, 19 Oct 2016 16:28:16 +0300 Message-Id: <20161019132816.31073-4-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161019132816.31073-1-georgi.djakov@linaro.org> References: <20161019132816.31073-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a driver for the A53 Clock Controller. It is a hardware block that implements a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated A53 PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on platforms like MSM8916. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/clock/qcom,a53cc.txt | 22 +++ drivers/clk/qcom/Kconfig | 8 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a53cc.c | 155 +++++++++++++++++++++ 4 files changed, 186 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53cc.txt create mode 100644 drivers/clk/qcom/a53cc.c diff --git a/Documentation/devicetree/bindings/clock/qcom,a53cc.txt b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt new file mode 100644 index 000000000000..a025f062f177 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt @@ -0,0 +1,22 @@ +Qualcomm A53 CPU Clock Controller Binding +------------------------------------------------ +The A53 CPU Clock Controller is hardware, which provides a combined +mux and divider functionality for the CPU clocks. It can choose between +a fixed rate clock and the dedicated A53 PLL. + +Required properties : +- compatible : shall contain: + + "qcom,a53cc" + +- reg : shall contain base register location and length + of the APCS region +- #clock-cells : shall contain 1 + +Example: + + apcs: syscon@b011000 { + compatible = "qcom,a53cc", "syscon"; + reg = <0x0b011000 0x1000>; + #clock-cells = <1>; + }; diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a889f0b14b54..59dfcdc340e4 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -159,3 +159,11 @@ config QCOM_A53PLL support for CPU frequencies above 1GHz. Say Y if you want to support CPU frequency scaling on devices such as MSM8916. + +config QCOM_A53CC + bool "A53 Clock Controller" + depends on COMMON_CLK_QCOM && QCOM_A53PLL + help + Support for the A53 clock controller on some Qualcomm devices. + Say Y if you want to support CPU frequency scaling on devices + such as MSM8916. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index d3e142e577b0..980a5d729aa4 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -30,4 +30,5 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53CC) += a53cc.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o diff --git a/drivers/clk/qcom/a53cc.c b/drivers/clk/qcom/a53cc.c new file mode 100644 index 000000000000..4d20db9da407 --- /dev/null +++ b/drivers/clk/qcom/a53cc.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2016, Linaro Limited + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include "clk-regmap.h" +#include "clk-regmap-mux-div.h" + +enum { + P_GPLL0, + P_A53PLL, +}; + +static const struct parent_map gpll0_a53cc_map[] = { + { P_GPLL0, 4 }, + { P_A53PLL, 5 }, +}; + +static const char * const gpll0_a53cc[] = { + "gpll0_vote", + "a53pll", +}; + +static const struct regmap_config a53cc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true, + .val_format_endian = REGMAP_ENDIAN_LITTLE, +}; + +static const struct of_device_id qcom_a53cc_match_table[] = { + { .compatible = "qcom,a53cc" }, + { } +}; + +/* + * We use the notifier function for switching to a temporary safe configuration + * (mux and divider), while the a53 pll is reconfigured. + */ +static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + int ret = 0; + struct clk_regmap_mux_div *md = container_of(nb, + struct clk_regmap_mux_div, + clk_nb); + + if (event == PRE_RATE_CHANGE) + ret = __mux_div_set_src_div(md, md->safe_src, md->safe_div); + + return notifier_from_errno(ret); +} + +static int qcom_a53cc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk_regmap_mux_div *a53cc; + struct resource *res; + void __iomem *base; + struct clk *pclk; + struct regmap *regmap; + struct clk_init_data init; + int ret; + + a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL); + if (!a53cc) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + a53cc->reg_offset = 0x50, + a53cc->hid_width = 5, + a53cc->hid_shift = 0, + a53cc->src_width = 3, + a53cc->src_shift = 8, + a53cc->safe_src = 4, + a53cc->safe_div = 3, + a53cc->parent_map = gpll0_a53cc_map, + + init.name = "a53mux", + init.parent_names = gpll0_a53cc, + init.num_parents = 2, + init.ops = &clk_regmap_mux_div_ops, + init.flags = CLK_SET_RATE_PARENT; + a53cc->clkr.hw.init = &init; + + pclk = __clk_lookup(gpll0_a53cc[1]); + if (!pclk) + return -EPROBE_DEFER; + + a53cc->clk_nb.notifier_call = a53cc_notifier_cb; + ret = clk_notifier_register(pclk, &a53cc->clk_nb); + if (ret) { + dev_err(dev, "failed to register clock notifier: %d\n", ret); + return ret; + } + + regmap = devm_regmap_init_mmio(dev, base, &a53cc_regmap_config); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(dev, "failed to init regmap mmio: %d\n", ret); + goto err; + } + + a53cc->clkr.regmap = regmap; + + ret = devm_clk_register_regmap(dev, &a53cc->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + goto err; + } + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &a53cc->clkr.hw); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + goto err; + } + + return 0; +err: + clk_notifier_unregister(pclk, &a53cc->clk_nb); + return ret; +} + +static struct platform_driver qcom_a53cc_driver = { + .probe = qcom_a53cc_probe, + .driver = { + .name = "qcom-a53cc", + .of_match_table = qcom_a53cc_match_table, + }, +}; + +builtin_platform_driver(qcom_a53cc_driver);