From patchwork Wed Jan 11 15:50:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 90925 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1185095qgi; Wed, 11 Jan 2017 07:50:42 -0800 (PST) X-Received: by 10.99.2.69 with SMTP id 66mr11591542pgc.68.1484149842658; Wed, 11 Jan 2017 07:50:42 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a67si6150685pfj.216.2017.01.11.07.50.42; Wed, 11 Jan 2017 07:50:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938388AbdAKPu3 (ORCPT + 25 others); Wed, 11 Jan 2017 10:50:29 -0500 Received: from mail-wj0-f180.google.com ([209.85.210.180]:34227 "EHLO mail-wj0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938373AbdAKPuY (ORCPT ); Wed, 11 Jan 2017 10:50:24 -0500 Received: by mail-wj0-f180.google.com with SMTP id tn15so105745778wjb.1 for ; Wed, 11 Jan 2017 07:50:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=WxFT1mkdtubh655hcd/nh/t1U+Tjfqcl8ib00Ajm6s0=; b=Zqi+BHhy3G3jgT57GCo0aEJMCrmCun16zoQBhvQMGgZs1axDsEF+k3tV7JJRrTDHIq +c9eKJLQin6mdb4/xZZSShaQ+jg+sPM+asiJhHok9SoLFTyDfWgfKhxW6Fx1QqZ5sxJo 674YZ0XTgLaNgvmd/1qYSEC4q7uuyNjsESJJU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WxFT1mkdtubh655hcd/nh/t1U+Tjfqcl8ib00Ajm6s0=; b=D5U8AZzP/t7N1Z7cA8lWZ4RO2Cv3mIZKr+kK1kSB8D4dJBqi8GYEbz1Q6VeJ1eWAa4 OU8KQJR0qguiokICRVMaQYOEVjoyQbdnnmVS/iK4LPLoDB5yF7p0ZXSqvCsQmT5TNzdZ E3GiTySMpxVk6u9Q9PTj3IAn69qeQwW3eLQnwLsSKC3mNs8IsfBA9nCuwOVsgZ2LJGV7 i6qpA6xPHnHP2bHGNDRl8xXfQRglvOOjOEacUIXvbIMPkPjaCJHJIVTP61IuHkDrzCqH Pt2jlWp6l+IcyQe9HwvHCou3fQKiK1OWMUMiJQNW3adsYV9iaZvqV0CJmZoafaQuMGub /Vzg== X-Gm-Message-State: AIkVDXIR4URFci2fUTZTjRq5o6ynTTo+TaTnJcp6rebeTCW4w6ZNnSIoXuC0ppc3zqAnW5ki X-Received: by 10.194.221.131 with SMTP id qe3mr6626086wjc.133.1484149823147; Wed, 11 Jan 2017 07:50:23 -0800 (PST) Received: from mms-0441.wifi.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id u78sm30418492wma.11.2017.01.11.07.50.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Jan 2017 07:50:21 -0800 (PST) From: Georgi Djakov To: andy.gross@linaro.org Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, mathieu.poirier@linaro.org, zhang.chunyan@linaro.org, iivanov.xz@gmail.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, georgi.djakov@linaro.org Subject: [PATCH v3] ARM: dts: qcom: Add apq8064 CoreSight components Date: Wed, 11 Jan 2017 17:50:21 +0200 Message-Id: <20170111155021.28273-1-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "Ivan T. Ivanov" Add initial set of CoreSight components found on Qualcomm apq8064 based platforms, including the IFC6410 board. Signed-off-by: Ivan T. Ivanov Acked-by: Mathieu Poirier Signed-off-by: Georgi Djakov --- Changes since v2 (https://lkml.org/lkml/2016/11/21/522) * Rebase to linux-next Changes since v1 (https://lkml.org/lkml/2016/11/17/474) * Moved everything into the SoC dtsi file as suggested by Stephen Boyd. * Updated commit message. * Got Ack from Mathieu. arch/arm/boot/dts/qcom-apq8064.dtsi | 189 +++++++++++++++++++++++++++++++++++- 1 file changed, 185 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 407a4610f4a7..4b77075ef731 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -28,7 +28,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + CPU0: cpu@0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; @@ -39,7 +39,7 @@ cpu-idle-states = <&CPU_SPC>; }; - cpu@1 { + CPU1: cpu@1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; @@ -50,7 +50,7 @@ cpu-idle-states = <&CPU_SPC>; }; - cpu@2 { + CPU2: cpu@2 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; @@ -61,7 +61,7 @@ cpu-idle-states = <&CPU_SPC>; }; - cpu@3 { + CPU3: cpu@3 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; @@ -1420,6 +1420,187 @@ }; }; }; + + etb@1a01000 { + compatible = "coresight-etb10", "arm,primecell"; + reg = <0x1a01000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etb_in: endpoint { + slave-mode; + remote-endpoint = <&replicator_out0>; + }; + }; + }; + + tpiu@1a03000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x1a03000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpiu_in: endpoint { + slave-mode; + remote-endpoint = <&replicator_out1>; + }; + }; + }; + + replicator { + compatible = "arm,coresight-replicator"; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + port@2 { + reg = <0>; + replicator_in: endpoint { + slave-mode; + remote-endpoint = <&funnel_out>; + }; + }; + }; + }; + + funnel@1a04000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x1a04000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Not described input ports: + * 2 - connected to STM component + * 3 - not-connected + * 6 - not-connected + * 7 - not-connected + */ + port@0 { + reg = <0>; + funnel_in0: endpoint { + slave-mode; + remote-endpoint = <&etm0_out>; + }; + }; + port@1 { + reg = <1>; + funnel_in1: endpoint { + slave-mode; + remote-endpoint = <&etm1_out>; + }; + }; + port@4 { + reg = <4>; + funnel_in4: endpoint { + slave-mode; + remote-endpoint = <&etm2_out>; + }; + }; + port@5 { + reg = <5>; + funnel_in5: endpoint { + slave-mode; + remote-endpoint = <&etm3_out>; + }; + }; + port@8 { + reg = <0>; + funnel_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + }; + + etm@1a1c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x1a1c000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + + port { + etm0_out: endpoint { + remote-endpoint = <&funnel_in0>; + }; + }; + }; + + etm@1a1d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x1a1d000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + + port { + etm1_out: endpoint { + remote-endpoint = <&funnel_in1>; + }; + }; + }; + + etm@1a1e000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x1a1e000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + + port { + etm2_out: endpoint { + remote-endpoint = <&funnel_in4>; + }; + }; + }; + + etm@1a1f000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x1a1f000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + + port { + etm3_out: endpoint { + remote-endpoint = <&funnel_in5>; + }; + }; + }; }; }; #include "qcom-apq8064-pins.dtsi"