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[209.132.180.67]) by mx.google.com with ESMTP id k5si41013pfa.417.2017.05.11.05.46.02; Thu, 11 May 2017 05:46:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932794AbdEKMpq (ORCPT + 25 others); Thu, 11 May 2017 08:45:46 -0400 Received: from mail-wr0-f178.google.com ([209.85.128.178]:36150 "EHLO mail-wr0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932443AbdEKMp3 (ORCPT ); Thu, 11 May 2017 08:45:29 -0400 Received: by mail-wr0-f178.google.com with SMTP id l50so19568715wrc.3 for ; Thu, 11 May 2017 05:45:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1kPcwTmlYGq9Erbg+ibjJGfNBPErz9QGCBeNSOhdbtk=; b=aUA5VKj42KVPeZJufIUSPNzTfi1uQ5w7+ISrAUsNbPCskUZtEzUeep2/rqw965BaP7 iIjhuO+vrW36z+0EO2GPErNrdC/ja+2s370eQhg+JoL1LbQSLdaRDdpQ0yN6wZOhRZdU oGDh0xjBQTvKwI3+TJsRUXClOkUfEaF0QMrWo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1kPcwTmlYGq9Erbg+ibjJGfNBPErz9QGCBeNSOhdbtk=; b=IcHWjmZCqq30OeCi+JpexC2O66rWPVygIv/a92DExo/BQ337AdvMlpubcBD8RvPNhT cEoMAF7TmD57JD1Q8Up3L08mdkNGUwMGyeXLVzKiqHjZx84SZwu0MolvAZ/ExFk2RSfR WmeeKIOav+3T8MpQ9+0zOGJyo7pfUgKBstZvp/Ywc4ns0XyeKxtUupDNB9yOzK8J0y89 GuPP+2ovM/eGT1R86eFRuRQFBV8XNPoj82VMwusQHI5qBClAYrXjZpLyQiq/4kLv6DFn SyFJzXh94iEPgC4w0Sjfl5hHJPgBBCdNHZE0SBTg+KM3EzR26IamuHk3j+rLoqQCZQL2 2yrw== X-Gm-Message-State: AODbwcC+iAr4EBx4PwYej62+4Om/y5I24F00V2Bduhbfcl5yeg+F5+Qu sQshzeDT1cPmtx/B X-Received: by 10.223.164.153 with SMTP id g25mr77829wrb.103.1494506727586; Thu, 11 May 2017 05:45:27 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id y16sm75643wry.46.2017.05.11.05.45.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 May 2017 05:45:25 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 27AEA3E0355; Thu, 11 May 2017 13:46:14 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, Zhichao Huang , =?utf-8?q?Alex_Benn=C3=A9e?= , Paolo Bonzini , =?utf-8?q?Radim_Kr=C4=8Dm?= =?utf-8?b?w6HFmQ==?= , Russell King , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 2/2] KVM: arm: rename pm_fake handler to trap_raz_wi Date: Thu, 11 May 2017 13:46:12 +0100 Message-Id: <20170511124612.11212-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170511124612.11212-1-alex.bennee@linaro.org> References: <20170511124612.11212-1-alex.bennee@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhichao Huang pm_fake doesn't quite describe what the handler does (ignoring writes and returning 0 for reads). As we're about to use it (a lot) in a different context, rename it with a (admitedly cryptic) name that make sense for all users. Signed-off-by: Zhichao Huang Reviewed-by: Alex Bennee Acked-by: Christoffer Dall Acked-by: Marc Zyngier Signed-off-by: Alex BennĂ©e --- v2: - fix minor merge conflicts - add maz a-b --- arch/arm/kvm/coproc.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) -- 2.11.0 diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c index c3ed6bd5ddf3..31bd9bb0b765 100644 --- a/arch/arm/kvm/coproc.c +++ b/arch/arm/kvm/coproc.c @@ -260,7 +260,7 @@ static bool access_gic_sre(struct kvm_vcpu *vcpu, * must always support PMCCNTR (the cycle counter): we just RAZ/WI for * all PM registers, which doesn't crash the guest kernel at least. */ -static bool pm_fake(struct kvm_vcpu *vcpu, +static bool trap_raz_wi(struct kvm_vcpu *vcpu, const struct coproc_params *p, const struct coproc_reg *r) { @@ -270,19 +270,19 @@ static bool pm_fake(struct kvm_vcpu *vcpu, return read_zero(vcpu, p); } -#define access_pmcr pm_fake -#define access_pmcntenset pm_fake -#define access_pmcntenclr pm_fake -#define access_pmovsr pm_fake -#define access_pmselr pm_fake -#define access_pmceid0 pm_fake -#define access_pmceid1 pm_fake -#define access_pmccntr pm_fake -#define access_pmxevtyper pm_fake -#define access_pmxevcntr pm_fake -#define access_pmuserenr pm_fake -#define access_pmintenset pm_fake -#define access_pmintenclr pm_fake +#define access_pmcr trap_raz_wi +#define access_pmcntenset trap_raz_wi +#define access_pmcntenclr trap_raz_wi +#define access_pmovsr trap_raz_wi +#define access_pmselr trap_raz_wi +#define access_pmceid0 trap_raz_wi +#define access_pmceid1 trap_raz_wi +#define access_pmccntr trap_raz_wi +#define access_pmxevtyper trap_raz_wi +#define access_pmxevcntr trap_raz_wi +#define access_pmuserenr trap_raz_wi +#define access_pmintenset trap_raz_wi +#define access_pmintenclr trap_raz_wi /* Architected CP15 registers. * CRn denotes the primary register number, but is copied to the CRm in the @@ -547,7 +547,7 @@ int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run) struct coproc_params params = decode_64bit_hsr(vcpu); /* raz_wi cp14 */ - pm_fake(vcpu, ¶ms, NULL); + trap_raz_wi(vcpu, ¶ms, NULL); /* handled */ kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); @@ -602,7 +602,7 @@ int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run) struct coproc_params params = decode_32bit_hsr(vcpu); /* raz_wi cp14 */ - pm_fake(vcpu, ¶ms, NULL); + trap_raz_wi(vcpu, ¶ms, NULL); /* handled */ kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));