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[209.132.180.67]) by mx.google.com with ESMTP id 33si168406plk.159.2017.06.14.01.25.33; Wed, 14 Jun 2017 01:25:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=c6k8/+VW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754716AbdFNIZV (ORCPT + 25 others); Wed, 14 Jun 2017 04:25:21 -0400 Received: from mail-pg0-f52.google.com ([74.125.83.52]:36488 "EHLO mail-pg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754431AbdFNIZN (ORCPT ); Wed, 14 Jun 2017 04:25:13 -0400 Received: by mail-pg0-f52.google.com with SMTP id a70so72554787pge.3 for ; Wed, 14 Jun 2017 01:25:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=c6k8/+VWrAMsAAaJTC+ki/2mZKyFh7JHSglprk24oHsZDDMvDcjuYpWLNhFRtzlKRC 1CERX4wK7VNiYmAUZO/33VQNSTCS2JREyMW019SknfpPhkunDL6ol27TWiBCfYGWYdCi W/L/kTuhzegou/d0MJmnw+ZbslLdV34jjzZuA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=oSPt0HB11PPUlsfZj+UCAa4jQWss6/5qgsVltvUgBIBruW0Ghftv/eEySGIBUKZBcd 8DbiA4uJdgqxVujt6D7y0Gs7EZzDwAAD1JQX/XxfXlyOjT59b4mlBQc8NXoLmSWty3mo LUKXoXt2vCy6MvB8H4pv0J6w+KVDkklWYEv90MODBWqwcutvgooleWcOUm6d2VCQLx+E RAMo44Zy6NYfqWWlbO7qaGXsiOOCf0iUYKbG+v/bAvi7YaGZ8rhOyn9HZG/038wWf5zf FFgE/nHc5NHiGDPuJDJuQ7dIOKe8O85OJVOVKKMnw1csEj6xuk2j1D+srxKG5TGUQsqH KeuA== X-Gm-Message-State: AKS2vOwCKtB4n5h8cFW5Io0Y3G3rhWvnTmkwx+iSIFofoR9bYpC9v+DY wvib9oQvFAfuv1OH X-Received: by 10.98.50.129 with SMTP id y123mr3000516pfy.53.1497428713240; Wed, 14 Jun 2017 01:25:13 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.25.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:25:12 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Leo Yan Subject: [PATCH v3 13/21] arm64: dts: hi3660: add sp804 timer node Date: Wed, 14 Jun 2017 16:23:30 +0800 Message-Id: <20170614082338.15673-14-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Leo Yan The Hi3660 SoC comes with the sp804 timer in addition to the architecture timers. These ones are shutdown when reaching a deep idle states and a backup timer is needed. The sp804 belongs to another power domain and can fulfill the purpose of replacing temporarily an architecture timer when the CPU is idle. Describe it in the device tree, so it can be enabled at boot time. Suggested-by: Daniel Lezcano Acked-by: Daniel Lezcano Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index a6b91f1..e138973 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -186,6 +186,17 @@ #reset-cells = <2>; }; + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = , + ; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + i2c0: i2c@ffd71000 { compatible = "snps,designware-i2c"; reg = <0x0 0xffd71000 0x0 0x1000>;