From patchwork Fri Jun 23 16:15:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 106272 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp289588qgd; Fri, 23 Jun 2017 09:16:04 -0700 (PDT) X-Received: by 10.99.143.9 with SMTP id n9mr9064046pgd.145.1498234564194; Fri, 23 Jun 2017 09:16:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498234564; cv=none; d=google.com; s=arc-20160816; b=doBgOoBFELJiIZDDNBW8PA6p/ECVenbtSGjQbVvx18NZiBrkuDGtLbXVDNarpICnsy 8YoSzAlrr5F6RvsGPC5PiL8vS/mLVK4BE1A8niK2nX329re54ZpgtgvwpulWVzFAfZic F73CGF+EJmkRS2ASKjwDYrQj0wqnfoNcZU6KA5HNKT/y2phi+RIQWh0zFKSwo8/jRzXc BccAakqP8RkPDtjv0eY77nPfdVnlEg+6Jl1CBAO4dY6gqhI3Pqco1Ao/w8GaDfJCSVDe ZCIv+6ftn+C0qY9C1W+iZ537SyqELaSYMZyyn1aW49nseQRu/QewfVpQiSt//1ODGjvL xBPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=To0mbXC9+TMuONrPF1DkHHK9QrR4PukQf+OGlGW0iq4=; b=q84EeUtFpCNj8yOA8ai8xkITXb40LOAOSWfPebvTgsATHtk7fdG1SEJVcuos8yjg1T 7kIOtFMzMMQnfY9XQbyUTfDyoogUA+PWUM5hdt3xAR6hhVoZlR+Uqd+awsDG3o6IGKIR FBf13+IW8m0MWTjSrlQkHdw4QBekR+gioW1fEg0j58Kkj4yxbc0Ypb4yL/O3k9z90Mnm mZWdArCLmtQ5zaP/6YWEJZZ+DI5ZVhGFIsNrmvmXKji23Iz4VBOYh2PxFc6ByqpbiAPr t41FZ/TNUuitZDTmj1X4fxLDOsmxj4FxBeA9mB7kgVvs0PfKnz/xOT51a5DZE7uzp1+Q 2r0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=Wxh0p6BG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m37si3884672plg.66.2017.06.23.09.16.03; Fri, 23 Jun 2017 09:16:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=Wxh0p6BG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754564AbdFWQPv (ORCPT + 25 others); Fri, 23 Jun 2017 12:15:51 -0400 Received: from mail-lf0-f54.google.com ([209.85.215.54]:34185 "EHLO mail-lf0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754471AbdFWQPl (ORCPT ); Fri, 23 Jun 2017 12:15:41 -0400 Received: by mail-lf0-f54.google.com with SMTP id l13so33779168lfl.1 for ; Fri, 23 Jun 2017 09:15:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=To0mbXC9+TMuONrPF1DkHHK9QrR4PukQf+OGlGW0iq4=; b=Wxh0p6BGTY4appKoAlz3OwOqVnlyt5bN/YCTpMlohBIbfdnpV9esRGT9dbV7FYcsHv KlViyiLw1bsXwJm0wJyXwNaQSgab4soeDf7zDLItGlpekYc6q9TvEcbQUnW/slq8rLfo N2wH2glXP2n/YPYjNHN9OH5kyFCdxUstnJFW0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=To0mbXC9+TMuONrPF1DkHHK9QrR4PukQf+OGlGW0iq4=; b=XG3CN0k64rZ9kat72ay4tfiRgGTAl9HSg3R3ac1O8u3Vu5aFWTWsSRpKRNwZm5gZmu C9fHdjsAf0QSlm2f1EQK0aKAbtzZcFT17Pt//Dro9jmNo3HPKjfcN+7gkcuH0DiNUvZG 8PfVQWYtcf3Hwy/Lt4KD6TKkUZ/q8Rbe+i7ftaJEmQHCaCHxw5T5SCx3WSqwyJW6tgty 87dmDbQsHiOEpyKdbSFVKysJhK7haQuaIpyAWBAf/h2qziYzWo+rLGOPuJGG6aW746AC FWlAG16BiOt1C2Tco4V3jSNE+2ogzNq6PFJ59CSK+60cDTEilZei0dsExBi6y5VRbQj+ bvgQ== X-Gm-Message-State: AKS2vOyyW9Odd8snk77rVlGXjk3mMsqPy2Udq5BD7Prj9I2PW8xxRocG 3tFwaXFl37ui+Xax X-Received: by 10.80.146.212 with SMTP id l20mr6628060eda.160.1498234539786; Fri, 23 Jun 2017 09:15:39 -0700 (PDT) Received: from mms-0441.qualcomm.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id c35sm2807711eda.13.2017.06.23.09.15.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 Jun 2017 09:15:39 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v8 3/3] mailbox: qcom: Add support for APCS clock controller Date: Fri, 23 Jun 2017 19:15:33 +0300 Message-Id: <20170623161533.20449-4-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170623161533.20449-1-georgi.djakov@linaro.org> References: <20170623161533.20449-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a driver for the APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on MSM8916-based platforms. Signed-off-by: Georgi Djakov --- .../bindings/mailbox/qcom,apcs-kpss-global.txt | 5 + drivers/mailbox/qcom-apcs-ipc-mailbox.c | 122 +++++++++++++++++++++ 2 files changed, 127 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt index fb961c310f44..2432be307083 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -21,6 +21,11 @@ platforms. Value type: Definition: as described in mailbox.txt, must be 1 +- #clock-cells: + Usage: required for msm8916 platforms + Value type: + Definition: as described in clock-bindings.txt, must be 0 + = EXAMPLE The following example describes the APCS HMSS found in MSM8996 and part of the diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 9924c6d7f05d..da363c6580da 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -11,6 +11,8 @@ * GNU General Public License for more details. */ +#include +#include #include #include #include @@ -19,6 +21,34 @@ #include #include #include +#include + +#include "../clk/qcom/clk-regmap.h" +#include "../clk/qcom/clk-regmap-mux-div.h" + +enum { + P_GPLL0, + P_A53PLL, +}; + +static const struct parent_map gpll0_a53cc_map[] = { + { P_GPLL0, 4 }, + { P_A53PLL, 5 }, +}; + +static const char * const gpll0_a53cc[] = { + "gpll0_vote", + "a53pll", +}; + +static const struct regmap_config a53cc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true, + .val_format_endian = REGMAP_ENDIAN_LITTLE, +}; #define QCOM_APCS_IPC_BITS 32 @@ -45,8 +75,93 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = { .send_data = qcom_apcs_ipc_send_data, }; +/* + * We use the notifier function for switching to a temporary safe configuration + * (mux and divider), while the A53 PLL is reconfigured. + */ +static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + int ret = 0; + struct clk_regmap_mux_div *md = container_of(nb, + struct clk_regmap_mux_div, + clk_nb); + if (event == PRE_RATE_CHANGE) + /* set the mux and divider to safe frequency (400mhz) */ + ret = __mux_div_set_src_div(md, 4, 3); + + return notifier_from_errno(ret); +} + +static int msm8916_register_clk(struct device *dev, void __iomem *base) +{ + struct clk_regmap_mux_div *a53cc; + struct clk *pclk; + struct regmap *regmap; + struct clk_init_data init = { }; + int ret; + + a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL); + if (!a53cc) + return -ENOMEM; + + a53cc->reg_offset = 0x50; + a53cc->hid_width = 5; + a53cc->hid_shift = 0; + a53cc->src_width = 3; + a53cc->src_shift = 8; + a53cc->parent_map = gpll0_a53cc_map; + + init.name = "a53mux"; + init.parent_names = gpll0_a53cc; + init.num_parents = 2; + init.ops = &clk_regmap_mux_div_ops; + init.flags = CLK_SET_RATE_PARENT; + a53cc->clkr.hw.init = &init; + + pclk = __clk_lookup(gpll0_a53cc[1]); + if (!pclk) + return -EPROBE_DEFER; + + a53cc->clk_nb.notifier_call = a53cc_notifier_cb; + ret = clk_notifier_register(pclk, &a53cc->clk_nb); + if (ret) { + dev_err(dev, "failed to register clock notifier: %d\n", ret); + return ret; + } + + regmap = devm_regmap_init_mmio(dev, base, &a53cc_regmap_config); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(dev, "failed to init regmap mmio: %d\n", ret); + goto err; + } + + a53cc->clkr.regmap = regmap; + + ret = devm_clk_register_regmap(dev, &a53cc->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + goto err; + } + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &a53cc->clkr.hw); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + goto err; + } + + return 0; + +err: + clk_notifier_unregister(pclk, &a53cc->clk_nb); + return ret; +} + static int qcom_apcs_ipc_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; struct qcom_apcs_ipc *apcs; struct resource *res; unsigned long offset; @@ -63,6 +178,13 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); + if (of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global")) { + /* register the APCS mux and divider clock */ + ret = msm8916_register_clk(&pdev->dev, base); + if (ret) + return ret; + } + offset = (unsigned long)of_device_get_match_data(&pdev->dev); apcs->reg = base + offset;