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[209.132.180.67]) by mx.google.com with ESMTP id i9si8336924pll.717.2017.08.21.09.05.18; Mon, 21 Aug 2017 09:05:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=EsWmTVyu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932195AbdHUQD6 (ORCPT + 26 others); Mon, 21 Aug 2017 12:03:58 -0400 Received: from mail-wr0-f175.google.com ([209.85.128.175]:32837 "EHLO mail-wr0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754478AbdHUQDX (ORCPT ); Mon, 21 Aug 2017 12:03:23 -0400 Received: by mail-wr0-f175.google.com with SMTP id 30so30556576wrk.0 for ; Mon, 21 Aug 2017 09:03:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pwhGKSiatDZIKAM4wyfDOdqR/aXoik20ct+gofTiRgA=; b=EsWmTVyuvmIMHotp0HOymvo8BAP5O4W1UO41uPtTcd+0mXb3/kC+7jiR3yQSBsv0Vk GZkJnd2NFjh7v/HYaTXSuBO4jJpo0SFXQN1frY1lK4Hat/gZkZlzZIue5thkSrupEUJH NNWYqOtznnRD3ILLlZwdu/1p/MiLMEIX80qecy/tEmtc/oxlQzyvZ3UPZAbVbUToWu+M mDB7Mfawl4FGX9kB0cry7M6ve338jvMvA78Zv2LzIHBWj17pPQkswZqe63v8MT4nW2Gb pyyw/0sO7oi5qPM567oxQ2tVDkh3QuI7TwMYgYaRjkEXvWoQbXmXs0cAahr3uD2I4SI1 FXrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pwhGKSiatDZIKAM4wyfDOdqR/aXoik20ct+gofTiRgA=; b=gX0oUZWwGXr2Lebd/6w3woodkfhO7oJXPj/svHEF+fBu06Ij34KGMCmM/x54iGS6C8 Qn4sBkey+x16iHX8DeNPtEnHQ4BZcRFQg7AbijCtm9xcsxRJ8PEztJZcK6Ee1WV1mFfz 3VU5Ry8+CrtgDAoOLcdLO5DTvmt1ezUE0TfHrt09Az5o+1DgNH/9CyzKqGu3bgk7Dw5A MdZAozWtUF6f0OtQUHmLgKgDuZs07AkBzDqO904lcWyEitmMgIuLHHgL5HGrg9hnNzF2 KNPTuMi8mG9Q4puR6VrVp4dkVKVp5Z0cKcLHqL9R1EB1D+HN/+oKH60ZhcYPGSzccrX7 YD0w== X-Gm-Message-State: AHYfb5i7XPQq+Qcevjh27KaNFbpzxDLKeUPQC0BA334y0gr8hV2COQBX BTXsxW/VS0NFwS+t X-Received: by 10.28.161.196 with SMTP id k187mr1898796wme.118.1503331401515; Mon, 21 Aug 2017 09:03:21 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 63sm8120063wra.30.2017.08.21.09.03.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 09:03:21 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 15/16] mmc: meson-gx: change default tx phase Date: Mon, 21 Aug 2017 18:03:00 +0200 Message-Id: <20170821160301.21899-16-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170821160301.21899-1-jbrunet@baylibre.com> References: <20170821160301.21899-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Initial default tx phase was set to 0 while the datasheet recommends 270. Some cards fails to initialize with this setting and eMMC mode DDR52 does not work. Changing this setting to 270 fixes these issues, without any regression so far Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.9.5 Reviewed-by: Kevin Hilman diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 3167f561e1a6..290631d46a4b 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -1158,8 +1158,14 @@ static int meson_mmc_probe(struct platform_device *pdev) if (ret) goto free_host; + /* + * Set phases : These values are mostly the datasheet recommended ones + * except for the Tx phase. Datasheet recommends 180 but some cards + * fail at initialisation with it. 270 works just fine, it fixes these + * initialisation issues and enable eMMC DDR52 mode. + */ host->tp.core_phase = 180; - host->tp.tx_phase = 0; + host->tp.tx_phase = 270; host->tp.rx_phase = 0; ret = meson_mmc_clk_init(host);