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[209.132.180.67]) by mx.google.com with ESMTP id i87si4554316pfd.457.2017.08.21.09.10.37; Mon, 21 Aug 2017 09:10:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=pcoCdDys; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754456AbdHUQKf (ORCPT + 26 others); Mon, 21 Aug 2017 12:10:35 -0400 Received: from mail-wr0-f170.google.com ([209.85.128.170]:38213 "EHLO mail-wr0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753546AbdHUQDJ (ORCPT ); Mon, 21 Aug 2017 12:03:09 -0400 Received: by mail-wr0-f170.google.com with SMTP id p8so39038137wrf.5 for ; Mon, 21 Aug 2017 09:03:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v2tkjLCmvtPUcXAXid7lD2gkivw1BrIsDeU4rrNjMuU=; b=pcoCdDysjHq98vqK6tNuJ+LKgVePstHsRynnrAqDKdeD7217bOrkwlayQzGzt+8A0X qwk6bHXQ76/Ucx5Hlg85QasvncML09L3VsU5tEWouubdJaXY586dIpXvrGjsHEY78UMd lx3k0iwjKYlpx8dzl2Xech9jBY56TrrHWK3ITpiS0uy+DNPupLmyhlE/XJ2KMGhzjM15 aOcD27haVOB0DmWNHqBRskYpOE8E7udJ8Wbd9HeIjwC4qGnULH/zr+yQzjAS1r4PUI6d OsQLIEGXIN5LMPGH1w2kU5+OLBdZAHhsF6DfuABH1F+s/xP6T1+U96mqscFY/DWo4Mcb deqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v2tkjLCmvtPUcXAXid7lD2gkivw1BrIsDeU4rrNjMuU=; b=TE2zEmRjiI1UFA+lr+g5Gj/ZmtrUOCdW8wbFQD4inY0Rzt0tu/wG9u7GqFmeWi8k8Z QNcHbdDa4Z4BTFHOjFkPfdBP2bF3sb9cwgljugE39a5jwnhm1IsYnuTSHb5ciqCinQS3 xNfoIH/72OCGcjms0vTnsLCoFkGFCSPlMCAV5VX7e1leu5l61jWRUcunecS8GQfTQQCM LCQy0kdNF9e6z3LfzPeWIbiNa8/czsl+OyTzd0VGLTRl6K7M0cmBsQkwzTHumGtgqlWO 1gw75k+VFs9097YjM/UQhFluTpRX3iMgzdZ56ZnCNXXoMnn0sidWZ8b7UkKXKBkTHFN7 N34g== X-Gm-Message-State: AHYfb5h/50GvJkgeaNPZWTnrab1OCXeO9P/jDG7m51S19uhjPX58NcgN HIp5rSHsQeFVRPDo X-Received: by 10.223.161.77 with SMTP id r13mr10856101wrr.53.1503331388642; Mon, 21 Aug 2017 09:03:08 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 63sm8120063wra.30.2017.08.21.09.03.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 09:03:08 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 03/16] mmc: meson-gx: clean up some constants Date: Mon, 21 Aug 2017 18:02:48 +0200 Message-Id: <20170821160301.21899-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170821160301.21899-1-jbrunet@baylibre.com> References: <20170821160301.21899-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove unused clock rate defines. These should not be defined but requested from the clock framework. Also correct typo on the DELAY register Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index d480a8052a06..8a74a048db88 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -45,9 +45,7 @@ #define CLK_DIV_MAX 63 #define CLK_SRC_MASK GENMASK(7, 6) #define CLK_SRC_XTAL 0 /* external crystal */ -#define CLK_SRC_XTAL_RATE 24000000 #define CLK_SRC_PLL 1 /* FCLK_DIV2 */ -#define CLK_SRC_PLL_RATE 1000000000 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) @@ -57,7 +55,7 @@ #define CLK_PHASE_270 3 #define CLK_ALWAYS_ON BIT(24) -#define SD_EMMC_DElAY 0x4 +#define SD_EMMC_DELAY 0x4 #define SD_EMMC_ADJUST 0x8 #define SD_EMMC_CALOUT 0x10 #define SD_EMMC_START 0x40