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[209.132.180.67]) by mx.google.com with ESMTP id s10si7605150pgp.757.2017.10.02.05.28.03; Mon, 02 Oct 2017 05:28:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=Ly/LP6Ou; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751420AbdJBM2B (ORCPT + 26 others); Mon, 2 Oct 2017 08:28:01 -0400 Received: from mail-wm0-f46.google.com ([74.125.82.46]:48007 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750984AbdJBM1y (ORCPT ); Mon, 2 Oct 2017 08:27:54 -0400 Received: by mail-wm0-f46.google.com with SMTP id t69so10238709wmt.2 for ; Mon, 02 Oct 2017 05:27:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7CkBvwonkVOhON/4HrCHr7vpIOloln4LXHTZU1V9M+I=; b=Ly/LP6OugtKsBEJqUB6thk54nVs7+uJesym12TluNXyAGxG2u3wTegAe2xWkj90f4t fLpOlBEbPM4xCHRUZEEYdvchtUYcu3d7+kTRTcf4UX0YZ8YDyrfJLmfS+VSaR9ljdHCU HBoheX7V6XQ8xC/KpTJrnPyGPexq8zvqkTMNl74Hj2d2zHeL+r+J8/BFywIeCK2XpBL/ k3Vxb/VwSrfuowhNfgSGCD3pNghawM5pHqOXKzpHv89ZFInsaHoRQQfCVOP7Hoyq4ap0 25YLn/bDPwM7sCQLMOyxOxEIvR3iC7MNIoKrCO5tK/ZMxkMCpqgzXQNqc9/tvubwiUhD NnAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7CkBvwonkVOhON/4HrCHr7vpIOloln4LXHTZU1V9M+I=; b=kgdd8Oarjo68Oe+WdR6HBj9SELxhP5Q+kWK75AceHlCE8XYQcfNOrQcMs9uNCyXH4O YHOmsVYfpW6/D2XyoCE1yVQ+hltLV4/loc4H8bohmzGCILsUR+O6bAITp9rK34et8gjJ /rVZBQN6hF/Wy1I8GYlPWY8xwpddpUN+5zLrKUCKvzj9u3TJhrHgU52aC5IQdyJS8rlu qeX9IulqchAF537X9byA0H2kbXHsDX3kt78GdQlpf7gFDa+aF+shp7+lM+ntJ7ucgYID T6eg5ZjAOxPpJYIwidGDsTaVLwUE1kFiqJ5COY54Wh2E5R0LJQqlxvOjESEK7Kbu5oOz eC3w== X-Gm-Message-State: AMCzsaWUlGkher8l2psWz93RozYlcg0ytCjy65kMkonWy/RSCOnrCiEz CNFsfQhk+3IqOY2sfTmudMTcxw== X-Google-Smtp-Source: AOwi7QAboVDXjWTEXcHQidweGkI7m75yu2L9f9aP91cUzd8Ic8tLeZIZ/e2noMkjA5azS6VDaZtXYQ== X-Received: by 10.28.196.79 with SMTP id u76mr7369024wmf.95.1506947273636; Mon, 02 Oct 2017 05:27:53 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id u96sm14354287wrc.68.2017.10.02.05.27.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Oct 2017 05:27:52 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , Heiner Kallweit , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] mmc: meson-gx: include tx phase in the tuning process Date: Mon, 2 Oct 2017 14:27:43 +0200 Message-Id: <20171002122743.32334-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171002122743.32334-1-jbrunet@baylibre.com> References: <20171002122743.32334-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It has been reported that some platforms (odroid-c2) may require a different tx phase setting to operate at high speed (hs200 and hs400) To improve the situation, this patch includes tx phase in the tuning process. Fixes: d341ca88eead ("mmc: meson-gx: rework tuning function") Reported-by: Heiner Kallweit Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) -- 2.13.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 08a55c2e96e1..85745ef179e2 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -716,6 +716,22 @@ static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode, static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) { struct meson_host *host = mmc_priv(mmc); + int ret; + + /* + * If this is the initial tuning, try to get a sane Rx starting + * phase before doing the actual tuning. + */ + if (!mmc->doing_retune) { + ret = meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk); + + if (ret) + return ret; + } + + ret = meson_mmc_clk_phase_tuning(mmc, opcode, host->tx_clk); + if (ret) + return ret; return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk); } @@ -746,8 +762,9 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (!IS_ERR(mmc->supply.vmmc)) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); - /* Reset rx phase */ + /* Reset phases */ clk_set_phase(host->rx_clk, 0); + clk_set_phase(host->tx_clk, 270); break;