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X-Host: mariner.tdc.vzwcorp.com Received: from ohtwi1exh002.uswin.ad.vzwcorp.com ([10.144.218.44]) by eris.verizonwireless.com with ESMTP/TLS/AES128-SHA256; 07 Oct 2017 22:37:00 +0000 Received: from tbwexch16apd.uswin.ad.vzwcorp.com (153.114.162.40) by OHTWI1EXH002.uswin.ad.vzwcorp.com (10.144.218.44) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sat, 7 Oct 2017 18:37:01 -0400 Received: from OMZP1LUMXCA13.uswin.ad.vzwcorp.com (144.8.22.188) by tbwexch16apd.uswin.ad.vzwcorp.com (153.114.162.40) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Sat, 7 Oct 2017 18:37:00 -0400 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com (144.8.22.195) by OMZP1LUMXCA13.uswin.ad.vzwcorp.com (144.8.22.188) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Sat, 7 Oct 2017 17:36:59 -0500 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) by OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) with mapi id 15.00.1263.000; Sat, 7 Oct 2017 17:36:59 -0500 To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" Subject: [PATCH review for 4.9 22/50] clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum Thread-Topic: [PATCH review for 4.9 22/50] clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum Thread-Index: AQHTP7zEUehRdGYDtU+qNiyFI1uQRA== Date: Sat, 7 Oct 2017 22:36:51 +0000 Message-ID: <20171007223636.24797-22-alexander.levin@verizon.com> References: <20171007223636.24797-1-alexander.levin@verizon.com> In-Reply-To: <20171007223636.24797-1-alexander.levin@verizon.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.144.60.250] MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ding Tianhong [ Upstream commit 729e55225b1f6225ee7a2a358d5141a3264627c4 ] This erratum describes a bug in logic outside the core, so MIDR can't be used to identify its presence, and reading an SoC-specific revision register from common arch timer code would be awkward. So, describe it in the device tree. Signed-off-by: Ding Tianhong Acked-by: Rob Herring Signed-off-by: Mark Rutland Signed-off-by: Daniel Lezcano Signed-off-by: Sasha Levin --- Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index ad440a2b8051..e926aea1147d 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. This also affects writes to the tval register, due to the implicit counter read. +- hisilicon,erratum-161010101 : A boolean property. Indicates the + presence of Hisilicon erratum 161010101, which says that reading the + counters is unreliable in some cases, and reads may return a value 32 + beyond the correct value. This also affects writes to the tval + registers, due to the implicit counter read. + ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize