From patchwork Thu Nov 23 12:11:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 119515 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp727072qgn; Thu, 23 Nov 2017 04:11:45 -0800 (PST) X-Google-Smtp-Source: AGs4zMZiuD/WX3aqRHgYIxXmC+DwS71vAj6jQ5Diu5+TuL27UJ35QW5Ge/I3ZRtFlVPB4R0kq/0z X-Received: by 10.84.171.129 with SMTP id l1mr13589489plb.438.1511439105727; Thu, 23 Nov 2017 04:11:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511439105; cv=none; d=google.com; s=arc-20160816; b=KvcyrgBcngEuxcpd2eWo8egZCze7ETiih6UCjvV+gfhngnQmlJepoBHP/vyzQyytID u/yprLDBRhntkCkqOF44Fhq73q1X+2p900OM2LB68srTiCATOHkExgi7E5ygtkIUUlKS dYB4qcqpY+zCSR1fuSCSjGu2kH4SzrebCcv6iQjZzl3d/6Zn8xJFGjxOTieHS7Qva8jJ y17AIxE/uQ0baXiut0YLbD/EgUw/RJXxQTygys2NrZJNe6Co5IHq71FS1/fF5Ce7l1DH Txz8bcdD/74BbPwDEkDLco/ddlUKpAFYnTEodcRXVKUmPMm9w+e6bvzTgsI3qOh4DmK1 tg4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=EYF0sMOBzBWqbkDMFpJz09wwUdXiuhAlZy37sizlgnU=; b=mW/Hk+gMU+H7OMrN/2jusfgvmQhKYKVXz2t7MAn+DKm2XiOmCkbaW2o4Ioj0MZE+04 g5+Wtx6fXWTGgIHAFBAdESVZOW6lRLvSDL7EBvbjXz4BRvcvzJyNbUdaqBk6ivuwe9nD /MCnXnkQ6V23XCwEzWsi6Vhb+8uTfT1DXqhn5/97xTILoOqyjbBSnLILsahTM6SrlQcT ejJXAkcZGjrrFSsrR3wk++2wNvkk76r7JgPauaiwyi9LyBCCoTKhdQFt1PtGRSlJkOhN GbfC5Tn04kOJEo9zpBBoks0eAom5NPMMB5REMNvlQLv27eHTT7KfAQFcjlChbbTfgepR /DQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NGRdthln; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m61si9745871plb.136.2017.11.23.04.11.45; Thu, 23 Nov 2017 04:11:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NGRdthln; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752734AbdKWMLn (ORCPT + 28 others); Thu, 23 Nov 2017 07:11:43 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:42432 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752242AbdKWMLk (ORCPT ); Thu, 23 Nov 2017 07:11:40 -0500 Received: by mail-wm0-f68.google.com with SMTP id l188so14694345wma.1 for ; Thu, 23 Nov 2017 04:11:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EYF0sMOBzBWqbkDMFpJz09wwUdXiuhAlZy37sizlgnU=; b=NGRdthlnLELYoxJeXnGv1ZrrHjWxGxr3dI3MSvPKgHfoK7THo0iSc4o381jTBjL4O8 arWFk3clA0uObzEXONIT8GBVk3AePBW+SIT1cCY65PZW6ucWlOqdI2bnP5GFYEHU1VoG CIAEjh7iA4iOMaPCNqY41uOAHu50m98PfLuuQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EYF0sMOBzBWqbkDMFpJz09wwUdXiuhAlZy37sizlgnU=; b=MUB6L+LITYXsJ5/LnycsNhP3E+sTx9IOITwvAP291zGePkQEBAFpEkdGO/r97d5g7T jYLA5vHMV2KVMY8XngGWrD4E4SeBo19oYOdh1ng2y8bmZlQtm+P2PhfcPItqJ5Nos5Wh JPIZXehkgrIor0E+mqK5efP5Uqi5gwV6DTFBGC7aocgw9+yyEqk/0XV6JFA7bGQrLop9 f8GlsojF54r9vMujBQpfaxTlnYIdk3IxpFQ789gnAoQcZxSiBl3cyT/MqDuqMmnWasGO bvL7xpxy3oVpldGz28rqYUNo2gLL0dY1zSSgZUZx52/OsymRchz0ocG9Clb0tOG9uj7N /Tyw== X-Gm-Message-State: AJaThX7kbDan6RGaQ1g2wb+//qPXdEbKS8ZehcFXQpQtuM+6+uE4vRzy ZV4VPWaNCLedfmjFD/W+N7NFEA== X-Received: by 10.28.105.14 with SMTP id e14mr6906849wmc.74.1511439098776; Thu, 23 Nov 2017 04:11:38 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id c3sm3914552wrf.21.2017.11.23.04.11.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Nov 2017 04:11:37 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id CBE833E009E; Thu, 23 Nov 2017 12:11:36 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: julien.thierry@arm.com, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Catalin Marinas , Will Deacon , Dave Martin , James Morse , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v1 2/2] kvm: arm64: handle single-step of hyp emulated mmio instructions Date: Thu, 23 Nov 2017 12:11:34 +0000 Message-Id: <20171123121134.11050-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171123121134.11050-1-alex.bennee@linaro.org> References: <20171123121134.11050-1-alex.bennee@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is a fast-path of MMIO emulation inside hyp mode. The handling of single-step is broadly the same as kvm_arm_handle_step_debug() except we just setup ESR/HSR so handle_exit() does the correct thing as we exit. For the case of an emulated illegal access causing an SError we will exit via the ARM_EXCEPTION_EL1_SERROR path in handle_exit(). We behave as we would during a real SError and clear the DBG_SPSR_SS bit for the emulated instruction. Signed-off-by: Alex Bennée --- arch/arm64/kvm/hyp/switch.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) -- 2.15.0 Reviewed-by: Christoffer Dall diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 525c01f48867..f7c651f3a8c0 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -22,6 +22,7 @@ #include #include #include +#include static bool __hyp_text __fpsimd_enabled_nvhe(void) { @@ -269,7 +270,11 @@ static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu) return true; } -static void __hyp_text __skip_instr(struct kvm_vcpu *vcpu) +/* Skip an instruction which has been emulated. Returns true if + * execution can continue or false if we need to exit hyp mode because + * single-step was in effect. + */ +static bool __hyp_text __skip_instr(struct kvm_vcpu *vcpu) { *vcpu_pc(vcpu) = read_sysreg_el2(elr); @@ -282,6 +287,14 @@ static void __hyp_text __skip_instr(struct kvm_vcpu *vcpu) } write_sysreg_el2(*vcpu_pc(vcpu), elr); + + if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { + vcpu->arch.fault.esr_el2 = + (ESR_ELx_EC_SOFTSTP_LOW << ESR_ELx_EC_SHIFT) | 0x22; + return false; + } else { + return true; + } } int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu) @@ -342,13 +355,21 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu) int ret = __vgic_v2_perform_cpuif_access(vcpu); if (ret == 1) { - __skip_instr(vcpu); - goto again; + if (__skip_instr(vcpu)) + goto again; + else + exit_code = ARM_EXCEPTION_TRAP; } if (ret == -1) { - /* Promote an illegal access to an SError */ - __skip_instr(vcpu); + /* Promote an illegal access to an + * SError. If we would be returning + * due to single-step clear the SS + * bit so handle_exit knows what to + * do after dealing with the error. + */ + if (!__skip_instr(vcpu)) + *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS; exit_code = ARM_EXCEPTION_EL1_SERROR; } @@ -363,8 +384,10 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu) int ret = __vgic_v3_perform_cpuif_access(vcpu); if (ret == 1) { - __skip_instr(vcpu); - goto again; + if (__skip_instr(vcpu)) + goto again; + else + exit_code = ARM_EXCEPTION_TRAP; } /* 0 falls through to be handled out of EL2 */