From patchwork Mon Nov 27 16:37:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 119747 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp512134qgn; Mon, 27 Nov 2017 08:38:53 -0800 (PST) X-Google-Smtp-Source: AGs4zMYRPqlqP3kDoTOhsnWuFJYjXpqd7v/Tk71b1WUJkoNQO9KyFIz7rGoPrtFK8khpGAYTz4K6 X-Received: by 10.101.74.8 with SMTP id s8mr36925336pgq.259.1511800733182; Mon, 27 Nov 2017 08:38:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511800733; cv=none; d=google.com; s=arc-20160816; b=SF6T5rdEqoYXVz800pU4327v4MFgP8NwONxqbw4Vtz0p/2DJiMuGHbemHKuTdQe1Eo eLr/PhaEJcF/y+GAtflauz8cJZc1FeqOLqt83ONRU//n6rHz09zRMhF9DpE+irWzInC9 FWNkP5N6awfv1LAitgpa+ZeKnvti0Lpx71YasE5P5FN1UTetD5AU5R5ZlVPOELrAOpT2 HFsuDso4T8+or2j2nm1lX3aQCOExutUo6OXeiuR01nPZkwki0icrzJ3h/2mZGMwMb3Vo y7FqYNgOn3rf8GET/TEYiVlwaNZSujzOa6tI8W+GSP2atErMLOZvgM892eJLcoEZFDpb b8Kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=+NI1W86NSLNpkwU0o7mDbhHP5wGI8yhTU21hMq8OCF0=; b=dXOXx807+ORa1/rspTDPIZvrX5154JfyCazJv2yY6NCx37ugkQyj0O7SiK6YKiGYTq ZBgdbKX6ae3p/4PmvC679sCgNA2HLvjyP1regmwCVPxxmdlj2amjrnVEuwwyeSUadciJ 0jej5ik3XLEDvKpnxkYiSwO/QySzJBWckcgZ7rFGyHLj5RNvidUJMKm564s5PLcYLOFs rBr3igbWO3CpeR/gl+V7KwgoNxK+K65CXlknuwCD2JXIO5bc2A38/vCT5/UJRQBFvRvK INanjq2S1pb4KLubJe2kSdkdWbbLQUAECD70hPBO/u2xat0FQn2BK5QsyuHh/5FdZz6g m01g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e28si22861932pgn.717.2017.11.27.08.38.52; Mon, 27 Nov 2017 08:38:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753642AbdK0Qiv (ORCPT + 28 others); Mon, 27 Nov 2017 11:38:51 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40094 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753599AbdK0Qit (ORCPT ); Mon, 27 Nov 2017 11:38:49 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A5D951529; Mon, 27 Nov 2017 08:38:49 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0E6F83F246; Mon, 27 Nov 2017 08:38:46 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, catalin.marinas@arm.com, cdall@linaro.org, kvmarm@lists.cs.columbia.edu, linux-arch@vger.kernel.org, marc.zyngier@arm.com, mark.rutland@arm.com, suzuki.poulose@arm.com, will.deacon@arm.com, yao.qi@arm.com, kernel-hardening@lists.openwall.com, linux-kernel@vger.kernel.org, awallis@codeaurora.org Subject: [PATCHv2 03/12] arm64/cpufeature: add ARMv8.3 id_aa64isar1 bits Date: Mon, 27 Nov 2017 16:37:57 +0000 Message-Id: <20171127163806.31435-4-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171127163806.31435-1-mark.rutland@arm.com> References: <20171127163806.31435-1-mark.rutland@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >From ARMv8.3 onwards, ID_AA64ISAR1 is no longer entirely RES0, and now has four fields describing the presence of pointer authentication functionality: * APA - address authentication present, using an architected algorithm * API - address authentication present, using an IMP DEF algorithm * GPA - generic authentication present, using an architected algorithm * GPI - generic authentication present, using an IMP DEF algorithm This patch adds the requisite definitions so that we can identify the presence of this functionality. For the timebeing, the features are hidden from both KVM guests and userspace. As marking them with FTR_HIDDEN only hides them from userspace, they are also protected with ifdeffery on CONFIG_ARM64_POINTER_AUTHENTICATION. Signed-off-by: Mark Rutland Cc: Suzuki K Poulose Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose --- arch/arm64/kernel/cpufeature.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.11.0 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c5ba0097887f..1883cdffcdf7 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -137,9 +137,17 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { +#ifdef CONFIG_ARM64_POINTER_AUTHENTICATION + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), +#endif ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), +#ifdef CONFIG_ARM64_POINTER_AUTHENTICATION + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0), +#endif ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), ARM64_FTR_END, };