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[209.132.180.67]) by mx.google.com with ESMTP id k8si23893167pgt.29.2017.11.27.23.20.06; Mon, 27 Nov 2017 23:20:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=RdNNVKJr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752028AbdK1HUE (ORCPT + 28 others); Tue, 28 Nov 2017 02:20:04 -0500 Received: from mail-pl0-f65.google.com ([209.85.160.65]:42887 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751256AbdK1HUC (ORCPT ); Tue, 28 Nov 2017 02:20:02 -0500 Received: by mail-pl0-f65.google.com with SMTP id z3so10132057plh.9; Mon, 27 Nov 2017 23:20:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=B9hlvz4fzbr3WeUqdM2yLJvbopNzwCUYsRjxegH1NzA=; b=RdNNVKJr2FBuvCPV8soSUR+e+pGVPhI25IrC4xMdZvgWlGbwZfxcbaBPueoqO+cCSt 1ihR6avUfnVWI/EZodYx7iYJvGKvSKICs6kGciRwTdFQWyYyjBxszEk1u3vEmJG6/Fmp waaEtVZIfBPymqrpyVC04dz8bEmAEOXpxE/nbqrRF5cVNF1ZOGqQt/dkyTrNI3CyDu51 eoygOX/e5MYzdd8zKO1mfjc7oFk5ZtZwGkcFlRoMljijN+/PDAbDaKCqRr13W0Fo/rkA 5PVTApAVWzbdiMnOOKDf28na+dEriDyQ9QmNaptxkbgWmAJVD9tta6vklkc+nYYEaOtc 5BWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=B9hlvz4fzbr3WeUqdM2yLJvbopNzwCUYsRjxegH1NzA=; b=ro/2fxfvfupzPKk0fo15ytocapeYhm8IhkJ/9omXf2zXX3NDegg9QZfolgs3O9jYnY /42+G3gmmqzc5Oc0q5o8YVPM50tgveDKjKpC5SRqJtzhih0vTMsh9bRkJl5z5J8vdQSj g2Loa1qOtoxJipje8OWq/Vwdr6MAAmF06wGs2+Vl/bAkm9WEOPhm6uND2SVjjKEG7Sow /CBtTfQHkNjaZkOGwb4OREjUk42rf+R7R2mhBhQYkNFoXcKb7Tf6yz0FjyFmYQEWbdaX To3gs6spx8QJyg/T2sRTpv2OnkdWZg7MbhY7FGwSpWw+9NN0xJYx/Ld9uElLcJKc+D20 W5dg== X-Gm-Message-State: AJaThX7+MWNlFkZq+z0EZInn4li2TxGHcEjueNcPY82WooEUGS0Ck/+G vvO8QfoxCJuypzf+Pp5O2M4qxfo27kU= X-Received: by 10.84.174.129 with SMTP id r1mr42338134plb.337.1511853602109; Mon, 27 Nov 2017 23:20:02 -0800 (PST) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id b10sm49348923pfj.20.2017.11.27.23.19.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Nov 2017 23:20:00 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 28 Nov 2017 17:49:53 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v6 3/5] clk: aspeed: Add platform driver and register PLLs Date: Tue, 28 Nov 2017 17:49:06 +1030 Message-Id: <20171128071908.12279-4-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171128071908.12279-1-joel@jms.id.au> References: <20171128071908.12279-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley -- v6: - Add Andrew's reviewed-by v5: - Remove eclk configuration. We do not have enough information to correctly implement the mux and divisor, so it will have to be implemented in the future v4: - Add eclk div table to fix ast2500 calculation - Add defines to document the BIT() macros - Pass dev where we can when registering clocks - Check for errors when registering clk_hws v3: - Fix bclk and eclk calculation - Separate out ast2400 and ast25000 for pll calculation --- drivers/clk/clk-aspeed.c | 130 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 9742f1d0977f..839243691b26 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -5,6 +5,8 @@ #include #include #include +#include +#include #include #include #include @@ -105,6 +107,18 @@ static const struct aspeed_gate_data aspeed_gates[] = { [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ }; +static const struct clk_div_table ast2500_mac_div_table[] = { + { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + static const struct clk_div_table ast2400_div_table[] = { { 0x0, 2 }, { 0x1, 4 }, @@ -170,6 +184,122 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) mult, div); } +struct aspeed_clk_soc_data { + const struct clk_div_table *div_table; + const struct clk_div_table *mac_div_table; + struct clk_hw *(*calc_pll)(const char *name, u32 val); +}; + +static const struct aspeed_clk_soc_data ast2500_data = { + .div_table = ast2500_div_table, + .mac_div_table = ast2500_mac_div_table, + .calc_pll = aspeed_ast2500_calc_pll, +}; + +static const struct aspeed_clk_soc_data ast2400_data = { + .div_table = ast2400_div_table, + .mac_div_table = ast2400_div_table, + .calc_pll = aspeed_ast2400_calc_pll, +}; + +static int aspeed_clk_probe(struct platform_device *pdev) +{ + const struct aspeed_clk_soc_data *soc_data; + struct device *dev = &pdev->dev; + struct regmap *map; + struct clk_hw *hw; + u32 val, rate; + + map = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + + /* SoC generations share common layouts but have different divisors */ + soc_data = of_device_get_match_data(dev); + if (!soc_data) { + dev_err(dev, "no match data for platform\n"); + return -EINVAL; + } + + /* UART clock div13 setting */ + regmap_read(map, ASPEED_MISC_CTRL, &val); + if (val & UART_DIV13_EN) + rate = 24000000 / 13; + else + rate = 24000000; + /* TODO: Find the parent data for the uart clock */ + hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; + + /* + * Memory controller (M-PLL) PLL. This clock is configured by the + * bootloader, and is exposed to Linux as a read-only clock rate. + */ + regmap_read(map, ASPEED_MPLL_PARAM, &val); + hw = soc_data->calc_pll("mpll", val); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; + + /* SD/SDIO clock divider (TODO: There's a gate too) */ + hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; + + /* MAC AHB bus clock divider */ + hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, + soc_data->mac_div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + + /* LPC Host (LHCLK) clock divider */ + hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; + + /* P-Bus (BCLK) clock divider */ + hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + + return 0; +}; + +static const struct of_device_id aspeed_clk_dt_ids[] = { + { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, + { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, + { } +}; + +static struct platform_driver aspeed_clk_driver = { + .probe = aspeed_clk_probe, + .driver = { + .name = "aspeed-clk", + .of_match_table = aspeed_clk_dt_ids, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(aspeed_clk_driver); + static void __init aspeed_ast2400_cc(struct regmap *map) { struct clk_hw *hw;