From patchwork Tue Nov 28 07:19:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 119800 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1358049qgn; Mon, 27 Nov 2017 23:20:16 -0800 (PST) X-Google-Smtp-Source: AGs4zMbtsQ4RPAGpPHIj/69auVdoe6A5ve0FpRj8tvtKVS7aLNYGLcOMwmeqx9dtYFpHhTu7NfWN X-Received: by 10.84.129.70 with SMTP id 64mr41522924plb.444.1511853616232; Mon, 27 Nov 2017 23:20:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511853616; cv=none; d=google.com; s=arc-20160816; b=TlxPuRRtoXSoNOPiGZnMvSRJ7ZeXIuCXCzSms/c2SgrzS0ge85ScSiEvZO/feO1aXm 7FmlnJHvKh012QLUReCSlH6thAIP0nyTAXC9BAdQ+RD+m9uYYLpAO1sSq0TP4ptdbw+9 DDoD6xtUxQgbn5CndoDcCKvNecCUwpfWe/fuB4/gJliOoqF6Hg3dEt4PGdPsyNuA7Zmj 8JDGKWLUxzsZl0mXvt/EsXrLNN8UmDxPe7EmsgKxyQ9Z2MwhqfGbFHl0fk8VrlM4UQik fKiYlq1ueJ+zm8M5+NNBBCQ0YEJKjj+cFBZaVeNvZ1JzAEthzF6LG2xhuEuY5O/9Ghsb 8iPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=A23Czos41//RZcbvNo1A4RY3+7Kf1myy5v3/nSvq9w0=; b=lF9rYJxQbEcwACsvihUW+zEb0xEKNDS4Qb3/JcVKr+m5tsMXsudBwbqy9KckHfh8AE OANT0NDZnLWEm5OesGeRoH56E8f2V9epAxCq1fHBTorsgXpVlvkHwoW69HqIxiOuPaBx EShduCOp1SZzbHGZ+dzq//T9K//ygptHxDdNLETFe7mzA4HI8Ztk0xN4/ngK9bFKNc1l 4NyqqKY/vnGlTPrqrEUp4vTsFcwWeZkN99jiObpG52DgiW8RdYgzjWvnf+SZxBrdG9ar Hkb7eJJd+pM79T/WgiRTK0ldKGN2/aBpk9KthBiLrxzwWUgnB0R8zzJM+0gnAjL5Pe+r UpKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=tNaS9Gly; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k8si23893167pgt.29.2017.11.27.23.20.15; Mon, 27 Nov 2017 23:20:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=tNaS9Gly; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752057AbdK1HUP (ORCPT + 28 others); Tue, 28 Nov 2017 02:20:15 -0500 Received: from mail-pg0-f67.google.com ([74.125.83.67]:36285 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751256AbdK1HUM (ORCPT ); Tue, 28 Nov 2017 02:20:12 -0500 Received: by mail-pg0-f67.google.com with SMTP id 199so8259148pgg.3; Mon, 27 Nov 2017 23:20:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=A23Czos41//RZcbvNo1A4RY3+7Kf1myy5v3/nSvq9w0=; b=tNaS9GlygH4AKb28rUqDmQO4M95EGfWnajz5uas58N7wKCJaKlDQuJJ2j1IZinTq4r 2lryagRxQeUmpa04rz+A4puGQIQJCJvq1ynQIZVYOqy9FPBAnHML+cEpfS1u9ebnRMIB 8PM36+YJX9r5oSi3ltyBn9N38Y6iuWNQWZzAzg9ff1LAPOSij5T6nTg72CtZ3FAo1vRp uhErpj1xZBYjKKsD82rXTVljR4UI0EQ9nsk4wwF8NPxe/2xI7JLxYeoK0jSxPn/s6a14 8YkyfCK7jnvAJaHiyLCwMJuAYNQ+z4e2JIKDwWTxkD260LRJzbESw5/Xcd1Hjzbz2UgL yoIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=A23Czos41//RZcbvNo1A4RY3+7Kf1myy5v3/nSvq9w0=; b=oqrfIEXzYsvarcVueIWPviiQKzudEMpyLVD07W7JVk7hWdR4Ji2w8IF+LEwD+9+NH7 Kdd8Iq0bGfGvM0LyYjPuWuKAMJ5GjpT3tetb4kMqKV4oXQDudFTHtZdP6xS4j8VLLjD8 EynWNx1KoDcbLrvc9ar7DSgsI2Lewa4B+qd7ngQQ7KyqbLq49eh8Fw6p5FqKCT5MDP8t JR/TvSEX3oIAwOXPuFg9vjASl+1WVurALdFpBTR62KKszMyGFknYwgEDWd9RZBy0jdIY 9MzgPoE8N4AfrQLPg6Ihf+sT4bUx5wgH9ykgEL1bpBrtVsm6XtK+41rlBtg4d0VSb2Os +c9w== X-Gm-Message-State: AJaThX5hb8iLdplLjzSBUT1jWTnQWmWOKtEhJ0ubKjtZIvDM1O1fSyTx 8rF5lg9vsW8nle9DddAom70= X-Received: by 10.99.160.100 with SMTP id u36mr39728443pgn.22.1511853611901; Mon, 27 Nov 2017 23:20:11 -0800 (PST) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id t62sm27116021pgt.23.2017.11.27.23.20.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Nov 2017 23:20:10 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 28 Nov 2017 17:50:02 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v6 4/5] clk: aspeed: Register gated clocks Date: Tue, 28 Nov 2017 17:49:07 +1030 Message-Id: <20171128071908.12279-5-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171128071908.12279-1-joel@jms.id.au> References: <20171128071908.12279-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The majority of the clocks in the system are gates paired with a reset controller that holds the IP in reset. This borrows from clk_hw_register_gate, but registers two 'gates', one to control the clock enable register and the other to control the reset IP. This allows us to enforce the ordering: 1. Place IP in reset 2. Enable clock 3. Delay 4. Release reset There are some gates that do not have an associated reset; these are handled by using -1 as the index for the reset. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- v5: - Add Andrew's Reviewed-by v4: - Drop useless 'disable clock' comment - Drop CLK_IS_BASIC flag - Fix 'there are a number of clocks...' comment - Pass device to clk registration functions - Check for errors when registering clk_hws v3: - Remove gates offset as gates are now at the start of the list --- drivers/clk/clk-aspeed.c | 131 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 839243691b26..b5dc3e298693 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -202,6 +202,107 @@ static const struct aspeed_clk_soc_data ast2400_data = { .calc_pll = aspeed_ast2400_calc_pll, }; +static int aspeed_clk_enable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = BIT(gate->clock_idx); + u32 rst = BIT(gate->reset_idx); + + spin_lock_irqsave(gate->lock, flags); + + if (gate->reset_idx >= 0) { + /* Put IP in reset */ + regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst); + + /* Delay 100us */ + udelay(100); + } + + /* Enable clock */ + regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, 0); + + if (gate->reset_idx >= 0) { + /* Delay 10ms */ + /* TODO: can we sleep here? */ + msleep(10); + + /* Take IP out of reset */ + regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0); + } + + spin_unlock_irqrestore(gate->lock, flags); + + return 0; +} + +static void aspeed_clk_disable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = BIT(gate->clock_idx); + + spin_lock_irqsave(gate->lock, flags); + + regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, clk); + + spin_unlock_irqrestore(gate->lock, flags); +} + +static int aspeed_clk_is_enabled(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + u32 clk = BIT(gate->clock_idx); + u32 reg; + + regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); + + return (reg & clk) ? 0 : 1; +} + +static const struct clk_ops aspeed_clk_gate_ops = { + .enable = aspeed_clk_enable, + .disable = aspeed_clk_disable, + .is_enabled = aspeed_clk_is_enabled, +}; + +static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + struct regmap *map, u8 clock_idx, u8 reset_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct aspeed_clk_gate *gate; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &aspeed_clk_gate_ops; + init.flags = flags; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + + gate->map = map; + gate->clock_idx = clock_idx; + gate->reset_idx = reset_idx; + gate->flags = clk_gate_flags; + gate->lock = lock; + gate->hw.init = &init; + + hw = &gate->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(gate); + hw = ERR_PTR(ret); + } + + return hw; +} + static int aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; @@ -209,6 +310,7 @@ static int aspeed_clk_probe(struct platform_device *pdev) struct regmap *map; struct clk_hw *hw; u32 val, rate; + int i; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -281,6 +383,35 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + /* + * TODO: There are a number of clocks that not included in this driver + * as more information is required: + * D2-PLL + * D-PLL + * YCLK + * RGMII + * RMII + * UART[1..5] clock source mux + * Video Engine (ECLK) mux and clock divider + */ + + for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { + const struct aspeed_gate_data *gd = &aspeed_gates[i]; + + hw = aspeed_clk_hw_register_gate(dev, + gd->name, + gd->parent_name, + gd->flags, + map, + gd->clock_idx, + gd->reset_idx, + CLK_GATE_SET_TO_DISABLE, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[i] = hw; + } + return 0; };