From patchwork Fri Dec 1 17:02:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 120366 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1391754qgn; Fri, 1 Dec 2017 09:03:59 -0800 (PST) X-Google-Smtp-Source: AGs4zMbO6g1WC8NsJE99Onwnn9YCVZJQq7Utmeddk5L/X4XHPB0pkf4QEJKhZEJZvn8MKUVzhdjY X-Received: by 10.84.133.111 with SMTP id 102mr6825814plf.136.1512147839466; Fri, 01 Dec 2017 09:03:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512147839; cv=none; d=google.com; s=arc-20160816; b=e0VdzyId3ulOKN1BK9A/WnMOKV3Kh1P19Ud1rtaA0+sPcexswxDc/qdtCyQ0Mq+pSx v5vnyZj3DXZk9qyVh6yPZDEAzcuuJKSQ0C7+x3aJvz6ECUu311prD15L3QpJyZbqarUP S0iXoXsB+hwPQW4/9EtOVXdEE2tB+MTAAT0JmBSmBex8jxqzxsv6swB+XB18fgSlzJz9 0Z2fqsmrj0dkOu0kNA9lAl982Z71TGoV9p6yCNZb0C2Wce/soyZB8UBwGbiczFafeyhJ ElIL2J86beCSZhEbQESiqDcvBWEHQKOL9WpHud7+8WYPAJiJ1T0AXVNntvbddMtCA3Ls djvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=1slH2e92voQPdezAs8CuA7K+8aK867LAOOcPdZ4FYTA=; b=B6zKB81BhOjT/ss4Mp76z5JL2QTuV/FhPQ4TguJBPK0IyoUCvcQ0PBgLvb90YTyaVy I6N7DZ3TmxjSrOWKNcjVN8DcJmHxXmENS6/iyErLhoH80JXwNfRk2S/NnBITCYJhzkrC 9kjrmJe96z4F8G8Y8e4DrdjdjrqjwqeIhRZ93ZXCSDejBrlryxOTypIdnE26YsA9FoBg l2SEIDU+6c7L2E2YNLWIHWEgSXe+LD3DNN4r217J/XGJhg2c0giJkqHanU8f2Mvj0+PV 1K1ciAxABFhuX0yAxCmxk0z+DaKQTa6Uxg2LvR/bawKsPkfNuoIuxEdAj6fB+K39u+07 h9Dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HCy4FtAu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v68si5061348pgv.557.2017.12.01.09.03.59; Fri, 01 Dec 2017 09:03:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HCy4FtAu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751855AbdLARD5 (ORCPT + 28 others); Fri, 1 Dec 2017 12:03:57 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:43763 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751265AbdLARCc (ORCPT ); Fri, 1 Dec 2017 12:02:32 -0500 Received: by mail-wm0-f67.google.com with SMTP id n138so4701335wmg.2 for ; Fri, 01 Dec 2017 09:02:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1slH2e92voQPdezAs8CuA7K+8aK867LAOOcPdZ4FYTA=; b=HCy4FtAu/pUJkKqesRDxPS/ZDO2HvaD4lU8c/E4YZ+p4RwVekqm0d8nExTVsNyfNRi XEGDyRkixVcfb7/ayq+uW7omekZS8IvB6b/gPV/e4koAKlcIyslue/kVNkbQzDjWhS/0 5vNBUQBuqZYJvB4PvJvRIPqWGGjTzkyGEf7Vo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1slH2e92voQPdezAs8CuA7K+8aK867LAOOcPdZ4FYTA=; b=tsWRdOmUfmTIOQUFmoBdt3Vb39R6T/0n+0B1gw+gcN6Uk8ANk/Y0a00rahCY6n0yiR qquh9GM96GBbjnAy1NxIs5rb5wqznIS6sRnzSdv09eQZt9q8DRPszsJe2VKUwCpYo3AR mUvxwQIOy0HbUbaFKF8rD1AQ3lQIfrEzB6nNzgwYpFx3yGaizqlmJ9CBi+v2yRj2Ft6k IoDRUwf3tNUDbTlBM+HgyuzxswHnc94Zqhx2TGLsyqoSrMNEPU+4cp/uT6Wq45X9Dngf +jptXAU1FaI6cZjNp2ZpA+PIgPKklGrZQDZ4cs4nB9GZC/Qpo2IyIPn0WFesmUGCyMEH vWvw== X-Gm-Message-State: AKGB3mLCDLnvj2tsGlbHEy/dFOBeVJWstn7VuHuHhc9dYk/9rBDRv+wq J1yZM/SfG5+NWJY8eXcg0cg5maSNgR4= X-Received: by 10.28.215.71 with SMTP id o68mr1643483wmg.105.1512147750592; Fri, 01 Dec 2017 09:02:30 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id 2sm1535253wmk.28.2017.12.01.09.02.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Dec 2017 09:02:29 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v10 3/6] clk: qcom: Add A53 PLL support Date: Fri, 1 Dec 2017 19:02:21 +0200 Message-Id: <20171201170224.25053-4-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org> References: <20171201170224.25053-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: Georgi Djakov Acked-by: Rob Herring --- .../devicetree/bindings/clock/qcom,a53pll.txt | 22 +++++ drivers/clk/qcom/Kconfig | 10 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a53-pll.c | 109 +++++++++++++++++++++ 4 files changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt create mode 100644 drivers/clk/qcom/a53-pll.c diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt new file mode 100644 index 000000000000..e3fa8118eaee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt @@ -0,0 +1,22 @@ +Qualcomm MSM8916 A53 PLL Binding +-------------------------------- +The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies +above 1GHz. + +Required properties : +- compatible : Shall contain only one of the following: + + "qcom,msm8916-a53pll" + +- reg : shall contain base register location and length + +- #clock-cells : must be set to <0> + +Example: + + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0xb016000 0x40>; + #clock-cells = <0>; + }; + diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 9f6c278deead..81ac7b9378fe 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -12,6 +12,16 @@ config COMMON_CLK_QCOM select REGMAP_MMIO select RESET_CONTROLLER +config QCOM_A53PLL + bool "MSM8916 A53 PLL" + depends on COMMON_CLK_QCOM + default ARCH_QCOM + help + Support for the A53 PLL on MSM8916 devices. It provides + the CPU with frequencies above 1GHz. + Say Y if you want to support higher CPU frequencies on MSM8916 + devices. + config QCOM_CLK_RPM tristate "RPM based Clock Controller" depends on COMMON_CLK_QCOM && MFD_QCOM_RPM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 26410d31446b..e767c60c24ec 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -32,5 +32,6 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c new file mode 100644 index 000000000000..b2bb8e9437f1 --- /dev/null +++ b/drivers/clk/qcom/a53-pll.c @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2017, Linaro Limited + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +#include "clk-pll.h" +#include "clk-regmap.h" + +static const struct pll_freq_tbl a53pll_freq[] = { + { 998400000, 52, 0x0, 0x1, 0 }, + { 1094400000, 57, 0x0, 0x1, 0 }, + { 1152000000, 62, 0x0, 0x1, 0 }, + { 1209600000, 63, 0x0, 0x1, 0 }, + { 1248000000, 65, 0x0, 0x1, 0 }, + { 1363200000, 71, 0x0, 0x1, 0 }, + { 1401600000, 73, 0x0, 0x1, 0 }, +}; + +static const struct regmap_config a53pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40, + .fast_io = true, +}; + +static int qcom_a53pll_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.of_node); + return 0; +} + +static int qcom_a53pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + struct resource *res; + struct clk_pll *pll; + void __iomem *base; + struct clk_init_data init = { }; + int ret; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + pll->l_reg = 0x04; + pll->m_reg = 0x08; + pll->n_reg = 0x0c; + pll->config_reg = 0x14; + pll->mode_reg = 0x00; + pll->status_reg = 0x1c; + pll->status_bit = 16; + pll->freq_tbl = a53pll_freq; + + init.name = "a53pll"; + init.parent_names = (const char *[]){ "xo" }; + init.num_parents = 1; + init.ops = &clk_pll_sr2_ops; + init.flags = CLK_IS_CRITICAL; + pll->clkr.hw.init = &init; + + ret = devm_clk_register_regmap(dev, &pll->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + return ret; + } + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll->clkr.hw); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id qcom_a53pll_match_table[] = { + { .compatible = "qcom,msm8916-a53pll" }, + { } +}; + +static struct platform_driver qcom_a53pll_driver = { + .probe = qcom_a53pll_probe, + .remove = qcom_a53pll_remove, + .driver = { + .name = "qcom-a53pll", + .of_match_table = qcom_a53pll_match_table, + }, +}; + +builtin_platform_driver(qcom_a53pll_driver);