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[209.132.180.67]) by mx.google.com with ESMTP id a28si3779900pgd.201.2017.12.07.06.27.28; Thu, 07 Dec 2017 06:27:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=w645etGN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753886AbdLGO11 (ORCPT + 22 others); Thu, 7 Dec 2017 09:27:27 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:36193 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753583AbdLGO1V (ORCPT ); Thu, 7 Dec 2017 09:27:21 -0500 Received: by mail-wr0-f195.google.com with SMTP id v105so7693222wrc.3 for ; Thu, 07 Dec 2017 06:27:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jbX9Qzt4ETVDloZ9SbBVmbstpUnZAlqiEZ57Kqs6F4I=; b=w645etGNuinIxb58yU/fXJUuJyspRXIykC1XBqhs1Ahih81a0BeJBO8JM1Ql1x7QBx s0ZuI/aX2DUZT9IpOn9YMeHqronR8yfPZq0g1pXIUsiu4zfsr4s5rZXiCCHiEar6fDp2 Jnyhf/0FUSl/+FYJvZ8nhcKRY+kHrAroYiSRZU4/VNbINGR5NlX5dq813YS7vmijhjAU 4mAKmKZOteBS7n/digM+eSWarNAqEOOmFaBA8Iyrd46+zFdVY4m5KidZFFtjniFGEial sV17EAiiuCFMRkVuRKMLoFOphA7h9TWzncrJFUUt+MWPpLPkvQ3xeAQKPzHTzy+MKYTj I3mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jbX9Qzt4ETVDloZ9SbBVmbstpUnZAlqiEZ57Kqs6F4I=; b=ANFUWugjKyTXl/JC8C4SAKfkPTComtPzjiGo2u8rNnbU56rt+yzps7d87cMTzAlgMj +jCGUVBetJHxdLiKqkB3ILoWJcobiOANcgdZSiIGOPH7ccWG3B3bfd8WR+NTWVWYO8cl f6ZP49M4UgDtJD421ZthvxqONMJRBMm+tYkzxhcvkChJ3cccKIEnCfAJZSPAdMRYG9Ia DU1iDWiPmfmfNqN19I5fmqd46kjsK6PZoz7O6JNbvRShW0GChvK1c453kq7xOGSjIGd2 MOh+9ntFGDj1Ig+a8SPUS6nWgxWDMrzws7kkU2hvcjJKKosg6mqK0Y9DA1DgMjS5qiBO 1KNw== X-Gm-Message-State: AJaThX7BglX1m2qo7k3KqHzrh4cLLmol5UeugaQMaO4AxYjR+UAaqUPi M/4NAibFcthZ+WjxfQeSWsoUYw== X-Received: by 10.223.186.202 with SMTP id w10mr25047315wrg.187.1512656840311; Thu, 07 Dec 2017 06:27:20 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id t138sm6264520wme.16.2017.12.07.06.27.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Dec 2017 06:27:19 -0800 (PST) From: Jerome Brunet To: Andrew Lunn , Florian Fainelli Cc: Jerome Brunet , Kevin Hilman , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong Subject: [PATCH net-next v2 2/8] net: phy: meson-gxl: define control registers Date: Thu, 7 Dec 2017 15:27:09 +0100 Message-Id: <20171207142715.32578-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171207142715.32578-1-jbrunet@baylibre.com> References: <20171207142715.32578-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Define registers and bits in meson-gxl PHY driver to make a bit more human friendly. No functional change. Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/net/phy/meson-gxl.c | 64 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 51 insertions(+), 13 deletions(-) -- 2.14.3 diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index 7ddb709f69fc..d82aa8cea401 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -22,54 +22,92 @@ #include #include #include +#include + +#define TSTCNTL 20 +#define TSTCNTL_READ BIT(15) +#define TSTCNTL_WRITE BIT(14) +#define TSTCNTL_REG_BANK_SEL GENMASK(12, 11) +#define TSTCNTL_TEST_MODE BIT(10) +#define TSTCNTL_READ_ADDRESS GENMASK(9, 5) +#define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0) +#define TSTREAD1 21 +#define TSTWRITE 23 + +#define BANK_ANALOG_DSP 0 +#define BANK_BIST 3 + +/* Analog/DSP Registers */ +#define A6_CONFIG_REG 0x17 + +/* BIST Registers */ +#define FR_PLL_CONTROL 0x1b +#define FR_PLL_DIV0 0x1c +#define FR_PLL_DIV1 0x1d static int meson_gxl_config_init(struct phy_device *phydev) { int ret; /* Enable Analog and DSP register Bank access by */ - ret = phy_write(phydev, 0x14, 0x0000); + ret = phy_write(phydev, TSTCNTL, 0); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x0400); + ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x0000); + ret = phy_write(phydev, TSTCNTL, 0); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x0400); + ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); if (ret) return ret; - /* Write Analog register 23 */ - ret = phy_write(phydev, 0x17, 0x8E0D); + /* Write CONFIG_A6*/ + ret = phy_write(phydev, TSTWRITE, 0x8e0d) if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x4417); + ret = phy_write(phydev, TSTCNTL, + TSTCNTL_WRITE + | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_ANALOG_DSP) + | TSTCNTL_TEST_MODE + | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, A6_CONFIG_REG)); if (ret) return ret; /* Enable fractional PLL */ - ret = phy_write(phydev, 0x17, 0x0005); + ret = phy_write(phydev, TSTWRITE, 0x0005); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x5C1B); + ret = phy_write(phydev, TSTCNTL, + TSTCNTL_WRITE + | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) + | TSTCNTL_TEST_MODE + | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_CONTROL)); if (ret) return ret; /* Program fraction FR_PLL_DIV1 */ - ret = phy_write(phydev, 0x17, 0x029A); + ret = phy_write(phydev, TSTWRITE, 0x029a); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x5C1D); + ret = phy_write(phydev, TSTCNTL, + TSTCNTL_WRITE + | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) + | TSTCNTL_TEST_MODE + | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV1)); if (ret) return ret; /* Program fraction FR_PLL_DIV1 */ - ret = phy_write(phydev, 0x17, 0xAAAA); + ret = phy_write(phydev, TSTWRITE, 0xaaaa); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x5C1C); + ret = phy_write(phydev, TSTCNTL, + TSTCNTL_WRITE + | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) + | TSTCNTL_TEST_MODE + | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV0)); if (ret) return ret;