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[209.132.180.67]) by mx.google.com with ESMTP id t3si8285170pgr.341.2017.12.18.01.46.42; Mon, 18 Dec 2017 01:46:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=bp5Qh+vt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933701AbdLRJqh (ORCPT + 28 others); Mon, 18 Dec 2017 04:46:37 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:44718 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758468AbdLRJoz (ORCPT ); Mon, 18 Dec 2017 04:44:55 -0500 Received: by mail-wm0-f66.google.com with SMTP id t8so27872257wmc.3 for ; Mon, 18 Dec 2017 01:44:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OLwJmgeUD3P0dRekE26KfH4G/1faj8pe7pF1iavmTnM=; b=bp5Qh+vtraz6gFkARC2xlkB3XZBffoPRg6A5GhcSQCgx1Auf3iUqTGRoIsJ70XKmpb pmsMYVN3PPaUM3lmior9JWUre/oZcoL6O47giNV859/MNF0+SeRXok5QnTRPHtxUhUZU gzQVG2XHbAcV4v2lyxxtSedEYneB9+wCJUTIXr6kqRxdvAFReuXFfXZjqRdmn2YZzXOj MS1+RIa749md4eRxsfAfGU5NYLa0j2jyqqsXwh7AO8R1YTNbsd7fKQsUZ2gPf8SV0swu 2lSKk/0RnLIUBYZ3qLNOD5C3LXu66aU/LqnuLTqlyr+maRuahWf9oQvFY1nIIg1Hn0bt x90A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OLwJmgeUD3P0dRekE26KfH4G/1faj8pe7pF1iavmTnM=; b=PPcvtypJqhwZ+I82j7Qos6m4sdWeqtA0f/+Crtr0GTkMq3EH2dgn3brScHBgzShlEE Ce3HLBXeRZgFHK02VMp5TvDHw0DHZwVtaE44yH8U5IobOBmhlhSgYXyg9QbLLoXVjN0H 8XU+Qy+RhFDvG92jPOzJ9eLUOyc21S6r4f0nWX/un7qEds9OnNrnG2U2Uj+r0X9/SB4M 2sTtx9hZhN1En37bZ4NHi/fQHvNgy0u+zSgfzoLVlMK8ctHOiwFkivinfbdgoEhY2oZR ii34P+FMMvnXa+vs2rVv6MtiXCmeJjUdcIi7SFiBi7d2DRduygT3xkB2YMP0XTm4xhaz 3ZrQ== X-Gm-Message-State: AKGB3mKUNJsJvcszsLPSRE47d83iVdiKrYdG1SCvvTRY4o4QeGNXd7YM nFf3a2U0B+xlD/Is6MvN42AeZg== X-Received: by 10.28.72.138 with SMTP id v132mr12537933wma.36.1513590294401; Mon, 18 Dec 2017 01:44:54 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id p13sm12820783wrc.61.2017.12.18.01.44.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 01:44:53 -0800 (PST) From: Jerome Brunet To: Andrew Lunn , Florian Fainelli Cc: Jerome Brunet , Kevin Hilman , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong Subject: [PATCH net-next v3 2/7] net: phy: meson-gxl: define control registers Date: Mon, 18 Dec 2017 10:44:41 +0100 Message-Id: <20171218094446.31912-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218094446.31912-1-jbrunet@baylibre.com> References: <20171218094446.31912-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Define registers and bits in meson-gxl PHY driver to make a bit more human friendly. No functional change. Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/net/phy/meson-gxl.c | 86 ++++++++++++++++++++++++++++++++++----------- 1 file changed, 66 insertions(+), 20 deletions(-) -- 2.14.3 diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index 900606204c0a..61bcc17098d7 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -24,53 +24,95 @@ #include #include +#define TSTCNTL 20 +#define TSTCNTL_READ BIT(15) +#define TSTCNTL_WRITE BIT(14) +#define TSTCNTL_REG_BANK_SEL GENMASK(12, 11) +#define TSTCNTL_TEST_MODE BIT(10) +#define TSTCNTL_READ_ADDRESS GENMASK(9, 5) +#define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0) +#define TSTREAD1 21 +#define TSTWRITE 23 + +#define BANK_ANALOG_DSP 0 +#define BANK_WOL 1 +#define BANK_BIST 3 + +/* Analog/DSP Registers */ +#define A6_CONFIG_REG 0x17 + +/* WOL Registers */ +#define LPI_STATUS 0xc +#define LPI_STATUS_RSV12 BIT(12) + +/* BIST Registers */ +#define FR_PLL_CONTROL 0x1b +#define FR_PLL_DIV0 0x1c +#define FR_PLL_DIV1 0x1d + static int meson_gxl_config_init(struct phy_device *phydev) { int ret; /* Enable Analog and DSP register Bank access by */ - ret = phy_write(phydev, 0x14, 0x0000); + ret = phy_write(phydev, TSTCNTL, 0); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x0400); + ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x0000); + ret = phy_write(phydev, TSTCNTL, 0); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x0400); + ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); if (ret) return ret; - /* Write Analog register 23 */ - ret = phy_write(phydev, 0x17, 0x8E0D); + /* Write CONFIG_A6*/ + ret = phy_write(phydev, TSTWRITE, 0x8e0d); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x4417); + ret = phy_write(phydev, TSTCNTL, + TSTCNTL_WRITE + | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_ANALOG_DSP) + | TSTCNTL_TEST_MODE + | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, A6_CONFIG_REG)); if (ret) return ret; /* Enable fractional PLL */ - ret = phy_write(phydev, 0x17, 0x0005); + ret = phy_write(phydev, TSTWRITE, 0x0005); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x5C1B); + ret = phy_write(phydev, TSTCNTL, + TSTCNTL_WRITE + | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) + | TSTCNTL_TEST_MODE + | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_CONTROL)); if (ret) return ret; /* Program fraction FR_PLL_DIV1 */ - ret = phy_write(phydev, 0x17, 0x029A); + ret = phy_write(phydev, TSTWRITE, 0x029a); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x5C1D); + ret = phy_write(phydev, TSTCNTL, + TSTCNTL_WRITE + | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) + | TSTCNTL_TEST_MODE + | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV1)); if (ret) return ret; /* Program fraction FR_PLL_DIV1 */ - ret = phy_write(phydev, 0x17, 0xAAAA); + ret = phy_write(phydev, TSTWRITE, 0xaaaa); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x5C1C); + ret = phy_write(phydev, TSTCNTL, + TSTCNTL_WRITE + | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) + | TSTCNTL_TEST_MODE + | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV0)); if (ret) return ret; @@ -105,26 +147,30 @@ static int meson_gxl_read_status(struct phy_device *phydev) goto read_status_continue; /* Need to access WOL bank, make sure the access is open */ - ret = phy_write(phydev, 0x14, 0x0000); + ret = phy_write(phydev, TSTCNTL, 0); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x0400); + ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x0000); + ret = phy_write(phydev, TSTCNTL, 0); if (ret) return ret; - ret = phy_write(phydev, 0x14, 0x0400); + ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); if (ret) return ret; /* Request LPI_STATUS WOL register */ - ret = phy_write(phydev, 0x14, 0x8D80); + ret = phy_write(phydev, TSTCNTL, + TSTCNTL_READ + | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_WOL) + | TSTCNTL_TEST_MODE + | FIELD_PREP(TSTCNTL_READ_ADDRESS, LPI_STATUS)); if (ret) return ret; /* Read LPI_STATUS value */ - wol = phy_read(phydev, 0x15); + wol = phy_read(phydev, TSTREAD1); if (wol < 0) return wol; @@ -136,7 +182,7 @@ static int meson_gxl_read_status(struct phy_device *phydev) if (exp < 0) return exp; - if (!(wol & BIT(12)) || + if (!(wol & LPI_STATUS_RSV12) || ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) { /* Looks like aneg failed after all */ phydev_dbg(phydev, "LPA corruption - aneg restart\n");