From patchwork Fri Feb 2 15:07:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 126728 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp726634ljc; Fri, 2 Feb 2018 07:09:01 -0800 (PST) X-Google-Smtp-Source: AH8x224JROM3yLKcgAokuCGIfV13rJmQcu2U5CIu6lzw4pG7Dlg6MASu9TlsRpSv5mYbQWsuJqb2 X-Received: by 10.99.67.133 with SMTP id q127mr32042719pga.365.1517584141272; Fri, 02 Feb 2018 07:09:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517584141; cv=none; d=google.com; s=arc-20160816; b=UJ48X2lUc5pF5Nnc1/nQFnqg+pV9sbp1h157EXQtUDWBjmBN5kxlemsXql6LqqtmmY FZfYS8D9qKUZyMUQzk6+A8lywMpVmSdV87xmXs0lXCadArQH2Uch+5ePcL5Gd2pvgvr1 NQ9vi9ix0b0EHhve/g0aqL0aKOaJVt3Z4KqxhMazxdhSwK6tRqCoeieltqiRFTMw7zsP M/OzolkB6NGxEfPOyzetkDpl46D55nlj+Mo3Eqc0nOJx05srE6ASJvNNw9aIfevm6vg+ 3zX5jDZDu+shAzk/rUAlqOf9RIk9aAEq8ZFrDqOHgCEtbCyGDOjigNJuXgXdSoFr8PKJ TgfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=pyhAg/dyMrB4R2G8qISnOBaSOMMciDfckAFCO+yrg2M=; b=KTJxRl+9ux2H553w3n7388BauHTQsw8iQTuxm2IC2ISyQk54Tel6kVTaXM2HocVHJa AH1fQrU8lC662f67AqXZNY1jMM/R5oc+n7+/uC+qiLlGWKAVkPq1NuJ9UaEkIHMPIDgs cPx8myU4ciczKALWtwdV5xzN9hRUqVIggtTL+lY48aRNWGvtD3Qf7vV80HT0gM/WwqDL JASo6fsxLZRnnhMjZn9dzrTpBCwl749wCTDxKan1ormXJu5jabWQS0etazdBa/PWQ/pQ 1ZRDVnhx5IYJUCVIYzQJhcy0Cl/srlpPxTJqjo5HbK/YBakYnQG/sW2fvJLmv0jZclWa quDA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n64si1971761pfb.184.2018.02.02.07.09.00; Fri, 02 Feb 2018 07:09:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752464AbeBBPI5 (ORCPT + 28 others); Fri, 2 Feb 2018 10:08:57 -0500 Received: from mout.kundenserver.de ([212.227.17.24]:57053 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752361AbeBBPIl (ORCPT ); Fri, 2 Feb 2018 10:08:41 -0500 Received: from wuerfel.lan ([95.208.111.237]) by mrelayeu.kundenserver.de (mreue104 [212.227.15.145]) with ESMTPA (Nemesis) id 0M4a32-1evxqW013U-00yfLL; Fri, 02 Feb 2018 16:08:16 +0100 From: Arnd Bergmann To: Russell King Cc: Nicolas Pitre , Andi Kleen , Richard Earnshaw , Tamar Christina , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] ARM: xscale: fix gcc-8 build Date: Fri, 2 Feb 2018 16:07:35 +0100 Message-Id: <20180202150756.420422-2-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20180202150756.420422-1-arnd@arndb.de> References: <20180202150756.420422-1-arnd@arndb.de> X-Provags-ID: V03:K0:2xE8Ysl+nge5G68+SZQ6I0gm8eZTMxRMNfb/OOim3hKtJxfhhnQ bebJdDMzeqhZ/v6tA0gomxUpE7lKLOlDpZdImYmhdOmE35PiiIzKNLxaf35HgM7r8zvTCqe uFS1Tz4IN5HcdRvn2Qj5w8zev63CRGTxt5ySXTw/qeMx35KjziEyTj0668OhAN1yJcrTUGg 5vU2V6F/iestPg0ZfIRpA== X-UI-Out-Filterresults: notjunk:1; V01:K0:3p06aYed3us=:CXvv4pWHrhIHFEYaL8/Sp/ Cpk68x+Ndu+I0dAL8/89yy5jiKXD2jTg//m6fWVPDN0YKAVnsfMe5qcsMwTQzLR94y3SrAD0L 5BbZ5QrUFvQ325KZ3UHRZUNqayRzUSg6SBM+F/b4Cj/2nJWbDGAEpIqtG4iDEXLhRLt3jfvTR Ykwgbf3nJ+dvgxGXayhpnWEY62/ou3FYDz9vVxrG+Cr8Xhy6+39XoFA4qZxSAl3UaSt/NQ5qL 4T5lqWhxTHnUz7at5tInKrMDdoa+1bWLwGnZe6CbGCoV7+f3xXzeAwz1V6JaxkCC87e3+mAEe 1AKnMIXd8czSziQNtAz8zOElnzpRcusPQkGyPZCYubX2gZWBaEv5TrEiKP0YypYGIlT30IB2t kKqqFvuTYtm53k8bPFK9xZdZg7RDqpCfIpQH0HF9UerRkuBsZuEouAUeWDXa8dgueLlzuN4CD ISMZWM0qfYhwwSbqOljMrHfteN4l1j/0NlzTwCjlNH1Ap09V6TJW4VQP9kpQaJFsOYcPbw5xq huPwrcEoAlg630z9LG/fUaYxGyhfgUaVxGO3EzWlfyX+MZXdCz6P6yT/aZwUi0cX6oFAmELN5 PlruUZn67yggaGG0vLymXFMYhRiFgl+39uCNvi3IYTD0Irql9rD2VCCHV7FGWf8fRqHC6+3vF 48xtR76ID2d7mJz7gPFBt8UF2sLYW/7DmQ32B34u/IatMrLaNTSezR7WYj4gRN0UpPbT7vSsg NM5g9EN7KgHwUbXWkm2JnP+FNjL6Zfcac8hI2g== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We use a hack in xscale-cp0.c to allow building it for ARMv4 while also using ARMv5TE and iWMMXt specific inline assembly, by adding a top-level asm statement. Unfortunately that hack no longer works with gcc-8, since it will revert back to the normal architecture. The recommended way of handling this is to use __attribute__((target("armv5te"))) on the functions that need it, or #pragma GCC target("arch=armv5te"). Either of those work with gcc-8, but not earlier versions, and it seems worse to combine that with the old hack. Instead, this adds the .arch statement to each inline assembler statement that needs it individually. That is also slightly uglier than the previous hack, but it works with all compiler versions and documents better why we need the override in the first place. Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84129 Signed-off-by: Arnd Bergmann --- arch/arm/kernel/xscale-cp0.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) -- 2.9.0 Acked-by: Nicolas Pitre diff --git a/arch/arm/kernel/xscale-cp0.c b/arch/arm/kernel/xscale-cp0.c index 77a2eef72115..e06a2f6dac4f 100644 --- a/arch/arm/kernel/xscale-cp0.c +++ b/arch/arm/kernel/xscale-cp0.c @@ -17,11 +17,10 @@ #include #include -asm(" .arch armv5te\n"); - static inline void dsp_save_state(u32 *state) { __asm__ __volatile__ ( + ".arch armv5te\n\t" "mrrc p0, 0, %0, %1, c0\n" : "=r" (state[0]), "=r" (state[1])); } @@ -29,6 +28,7 @@ static inline void dsp_save_state(u32 *state) static inline void dsp_load_state(u32 *state) { __asm__ __volatile__ ( + ".arch armv5te\n\t" "mcrr p0, 0, %0, %1, c0\n" : : "r" (state[0]), "r" (state[1])); } @@ -134,7 +134,8 @@ static int __init cpu_has_iwmmxt(void) * tmrrc %0, %1, wR0 */ __asm__ __volatile__ ( - "mcrr p0, 0, %2, %3, c0\n" + ".arch armv5te\n\t" + "mcrr p0, 0, %2, %3, c0\n\t" "mrrc p0, 0, %0, %1, c0\n" : "=r" (lo), "=r" (hi) : "r" (0), "r" (0x100));