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[209.132.180.67]) by mx.google.com with ESMTP id y11-v6si350293plg.498.2018.02.28.10.16.07; Wed, 28 Feb 2018 10:16:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NuI0ju/D; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932521AbeB1SP7 (ORCPT + 28 others); Wed, 28 Feb 2018 13:15:59 -0500 Received: from mail-pl0-f67.google.com ([209.85.160.67]:39155 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932451AbeB1SPy (ORCPT ); Wed, 28 Feb 2018 13:15:54 -0500 Received: by mail-pl0-f67.google.com with SMTP id s13-v6so1993429plq.6 for ; Wed, 28 Feb 2018 10:15:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uAx1vA24Mq41TzpmYpXGvaJ+GYIPjxEfE3ErymFJ74M=; b=NuI0ju/DHpGTDPtD7tyyUUMq+kV0rBs58C7SJAE2Cl0nuTXaql77qvK9+yhXY9sM+r 1N0+Tivp4ust7szLuE6TrN89u/NT8m9euzhbwUFfZrkoTzCampPAckOPjSkqy/PFv5or H/uqeFU4gzwL9kA1PJ6kP8Oq7JOWwcKzpqUs4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uAx1vA24Mq41TzpmYpXGvaJ+GYIPjxEfE3ErymFJ74M=; b=MTZXjyDQEIVJ/fNvgMSa/lfT6m3vsHAlh2ki6vLz8LrsXUQqFTb8IwGh1pp51jSlKR vNh/4NlgJ+3VX+L4A3a6ccUG1kKQRYlYbKCR2Mx95ZRpWN9mLeNm+1ibcu1sIW8oNaRB 2EkIBdvYaB30IPCYe9AfSACHIYfLKFsdeR7jMQi1n98U/JU5mInQGdDBgH2fTdzm30HS 4U4ROotfmyY4eSFDvycs2wmDwYgEpb+xHhHe9gHGyLokwaKUsKe9SUm/CKf17op8Ot/P kChpkLvGkCGO1WlYZQ3q+p6ey1y0oddZRt8iJpF9ZOOIj4eM9T0pekH++f1FfREkNa8l BCkw== X-Gm-Message-State: APf1xPDBAacUJvtEcKvzvNmAPsGl8ut+yfwPsK657gVNwmGv/auMdfJf FKYDBUp4laE8oBu0DbFn/gYL X-Received: by 2002:a17:902:ab88:: with SMTP id f8-v6mr19145078plr.325.1519841753553; Wed, 28 Feb 2018 10:15:53 -0800 (PST) Received: from localhost.localdomain ([2405:204:7380:867e:a4dd:d27b:1244:f453]) by smtp.gmail.com with ESMTPSA id u27sm4980258pfk.172.2018.02.28.10.15.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 10:15:52 -0800 (PST) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v3 05/10] dt-bindings: gpio: Add gpio nodes for Actions S900 SoC Date: Wed, 28 Feb 2018 23:44:27 +0530 Message-Id: <20180228181432.26847-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180228181432.26847-1-manivannan.sadhasivam@linaro.org> References: <20180228181432.26847-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add gpio nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/gpio/actions,owl-gpio.txt | 95 ++++++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/actions,owl-gpio.txt -- 2.14.1 diff --git a/Documentation/devicetree/bindings/gpio/actions,owl-gpio.txt b/Documentation/devicetree/bindings/gpio/actions,owl-gpio.txt new file mode 100644 index 000000000000..d2939ca6cfaf --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/actions,owl-gpio.txt @@ -0,0 +1,95 @@ +* Actions Semi OWL GPIO controller bindings + +The GPIOs are organized as individual banks/ports with variable number +of GPIOs. Each bank is represented as an individual GPIO controller. + +Required properties: +- compatible : Should be "actions,s900-gpio" +- reg : Address and range of the GPIO controller registers. +- gpio-controller : Marks the device node as a GPIO controller. +- #gpio-cells : Should be <2>. The first cell is the gpio number + and the second cell is used to specify optional + parameters. +- interrupt-controller : Marks the device node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt. Shall be set to 2. The first cell + defines the interrupt number, the second encodes + the trigger flags described in + bindings/interrupt-controller/interrupts.txt + +Optional properties: +- gpio-ranges : Mapping between GPIO and pinctrl + +Note: Each GPIO port should have an alias correctly numbered in "aliases" +node. + +Examples: + +aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; +}; + + gpioa: gpioa@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpiob: gpiob@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpioc: gpioc@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 12>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpiod: gpiod@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 76 30>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpioe: gpioe@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 106 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpiof: gpiof@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 138 8>; + interrupt-controller; + #interrupt-cells = <2>; + };