From patchwork Fri Mar 2 05:48:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 130466 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp906311lja; Thu, 1 Mar 2018 21:50:54 -0800 (PST) X-Google-Smtp-Source: AG47ELvktxyaaBkcBAN8k7Hd0lnX6n0CxwPcIunHge6JcfzEgzJnSVWBOIFq+SuRzzRlcIBI3dRI X-Received: by 2002:a17:902:6805:: with SMTP id h5-v6mr4284651plk.46.1519969853927; Thu, 01 Mar 2018 21:50:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519969853; cv=none; d=google.com; s=arc-20160816; b=Vb3cqTsYsU8AFeLWucj80zv2M+65ys6aZh5GLcn8bJ22tQSwPt/K3qZafyyUcFFuI/ G9JjMNmoUOkDVJbKSAShR9OfYom2tuiePzPJp4hjtaPSK3Cgmoj6Nxh2eA5NuGvNVgvm cyAEZFyz+Qed2kojWJfJETuIHGq+re3Ge18ofhmhoiT8ADFbqGRaivRIsHb0mJYLGVWM NjSQ3N5ABHhPqp5xi/z1Q3zfTcqdnb9WYZRqmHqAD0oQz4+i53s1FaiGV+IxXC+I4tMi rehedr2jzmiUQABU9yu8EDJIznpGgVUBUidfdq0OrBcbQNmu9YhBCFhitUueoFNlQlqt aN8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=GrFMhbR7yKiv60oRzhy3QPFqVk1Xitp7DmvnvpUrF60=; b=KIuXQKBPDyPaAUpZsK5V+DGGk1aLJnmMHI5hUKyQt/Mu5/Qws6wYG5KHisQ/pNQU02 ddEOLdTatkRt4trNzs6+mdQRqEnULJ9JN6i+rdpjMWHt/UL8VI823W4xrf/PtEiUdzB6 OS7EsMbE6IraqSepAdwlROhT0Viq7lmWdb3Mw8R+cVgtpakFW/nSvTZtLx33hmIARXZ8 H0Nf5a2VxMZfH7d5cJCtf1BPOphdbTdN0vD/QSpX1qb30DfG1O1tjs2QJzBRlXz1jCwq +O+E0alqADDAL6ivEromAXQk+5fe5cDpzsVxiuzC+Bok1gffVWOytFWb+HHkL4NGNuUT H2iw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ic139zMu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d14si3524617pgn.306.2018.03.01.21.50.53; Thu, 01 Mar 2018 21:50:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ic139zMu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935931AbeCBFuo (ORCPT + 28 others); Fri, 2 Mar 2018 00:50:44 -0500 Received: from mail-pl0-f65.google.com ([209.85.160.65]:43605 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935916AbeCBFuj (ORCPT ); Fri, 2 Mar 2018 00:50:39 -0500 Received: by mail-pl0-f65.google.com with SMTP id f23-v6so5088431plr.10 for ; Thu, 01 Mar 2018 21:50:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GrFMhbR7yKiv60oRzhy3QPFqVk1Xitp7DmvnvpUrF60=; b=Ic139zMut8BHgPEqFdXo8R0iYQVZZ760hInQ3Gc02AmeggmippoTbcM/0MaORcYDRf d8DG4tIC3xT1qeEvg9mSRxSbMkRAvxALaiT00GWZwMVtEFtnUOm9BUxGhJ0Wa/uwpeVt 56NIU2LEsgwI2gQTLIweoRdbnc+OxR7DahvRc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GrFMhbR7yKiv60oRzhy3QPFqVk1Xitp7DmvnvpUrF60=; b=Um34gqpt89rDd8ZRgW5uMzGwRKe4z/9UI3zPzrfdPUC4PBjRn8s4LEG6pD1t05LAk6 a7HXhOLTIIXjIM+xaOqqSIQMWJH93nXsmuWcABkc38CHzqvzv/lGQRm4XIlJAkJEPS5M 7I0I0Wx1IZIV2zE5BbhUQF+IUmMTOE09ef0ZdW8Z5Bn9uA9Tk2bWeUfBiZXuK1PIw7cG DZjgD3fxb/VtD/o8AcrAyWQgi1qeDaYsCArlMynID+qD3aTH8EAiRJyjTwoZMjPPwchx g0ophsyD1LCxCgMkGTlyKNXv6Dj2co0aFILR7QzCBphIzXYWHMlEY3bJTqhM0xS3YItv pRPA== X-Gm-Message-State: APf1xPAS8KxL/IgD9Vdy9ZAh8ja+zz9CN8fyWh+DuNVGNRO3gDkJdLq1 mtEgKMG3FbqUwZSiqy/em/XI X-Received: by 2002:a17:902:8349:: with SMTP id z9-v6mr4184479pln.163.1519969838754; Thu, 01 Mar 2018 21:50:38 -0800 (PST) Received: from localhost.localdomain ([2405:204:71c0:7f9a:bd87:b648:dccb:cbc9]) by smtp.gmail.com with ESMTPSA id t63sm12569748pfj.44.2018.03.01.21.50.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Mar 2018 21:50:38 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v4 01/11] dt-bindings: clock: Add Actions S900 clock bindings Date: Fri, 2 Mar 2018 11:18:50 +0530 Message-Id: <20180302054900.11275-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180302054900.11275-1-manivannan.sadhasivam@linaro.org> References: <20180302054900.11275-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Actions Semi S900 clock bindings. Signed-off-by: Manivannan Sadhasivam Acked-by: Rob Herring --- .../devicetree/bindings/clock/actions,s900-cmu.txt | 47 ++++++++ include/dt-bindings/clock/actions,s900-cmu.h | 129 +++++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/actions,s900-cmu.txt create mode 100644 include/dt-bindings/clock/actions,s900-cmu.h -- 2.14.1 diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt new file mode 100644 index 000000000000..93e4fb827cd6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt @@ -0,0 +1,47 @@ +* Actions S900 Clock Management Unit (CMU) + +The Actions S900 clock management unit generates and supplies clock to various +controllers within the SoC. The clock binding described here is applicable to +S900 SoC. + +Required Properties: + +- compatible: should be "actions,s900-cmu" +- reg: physical base address of the controller and length of memory mapped + region. +- clocks: Reference to the parent clocks ("hosc", "losc") +- #clock-cells: should be 1. + +Each clock is assigned an identifier, and client nodes can use this identifier +to specify the clock which they consume. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/actions,s900-cmu.h header and can be used in device +tree sources. + +External clocks: + +The hosc clock used as input for the plls is generated outside the SoC. It is +expected that it is defined using standard clock bindings as "hosc". + +Actions S900 CMU also requires one more clock: + - "losc" - internal low frequency oscillator + +Example: Clock Management Unit node: + + cmu: clock-controller@e0160000 { + compatible = "actions,s900-cmu"; + reg = <0x0 0xe0160000 0x0 0x1000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + +Example: UART controller node that consumes clock generated by the clock +management unit: + + uart: serial@e012a000 { + compatible = "actions,s900-uart", "actions,owl-uart"; + reg = <0x0 0xe012a000 0x0 0x2000>; + interrupts = ; + clocks = <&cmu CLK_UART5>; + }; diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h new file mode 100644 index 000000000000..7c1251565f43 --- /dev/null +++ b/include/dt-bindings/clock/actions,s900-cmu.h @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Device Tree binding constants for Actions Semi S900 Clock Management Unit +// +// Copyright (c) 2014 Actions Semi Inc. +// Copyright (c) 2018 Linaro Ltd. + +#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H +#define __DT_BINDINGS_CLOCK_S900_CMU_H + +#define CLK_NONE 0 + +/* fixed rate clocks */ +#define CLK_LOSC 1 +#define CLK_HOSC 2 + +/* pll clocks */ +#define CLK_CORE_PLL 3 +#define CLK_DEV_PLL 4 +#define CLK_DDR_PLL 5 +#define CLK_NAND_PLL 6 +#define CLK_DISPLAY_PLL 7 +#define CLK_DSI_PLL 8 +#define CLK_ASSIST_PLL 9 +#define CLK_AUDIO_PLL 10 + +/* system clock */ +#define CLK_CPU 15 +#define CLK_DEV 16 +#define CLK_NOC 17 +#define CLK_NOC_MUX 18 +#define CLK_NOC_DIV 19 +#define CLK_AHB 20 +#define CLK_APB 21 +#define CLK_DMAC 22 + +/* peripheral device clock */ +#define CLK_GPIO 23 + +#define CLK_BISP 24 +#define CLK_CSI0 25 +#define CLK_CSI1 26 + +#define CLK_DE0 27 +#define CLK_DE1 28 +#define CLK_DE2 29 +#define CLK_DE3 30 +#define CLK_DSI 32 + +#define CLK_GPU 33 +#define CLK_GPU_CORE 34 +#define CLK_GPU_MEM 35 +#define CLK_GPU_SYS 36 + +#define CLK_HDE 37 +#define CLK_I2C0 38 +#define CLK_I2C1 39 +#define CLK_I2C2 40 +#define CLK_I2C3 41 +#define CLK_I2C4 42 +#define CLK_I2C5 43 +#define CLK_I2SRX 44 +#define CLK_I2STX 45 +#define CLK_IMX 46 +#define CLK_LCD 47 +#define CLK_NAND0 48 +#define CLK_NAND1 49 +#define CLK_PWM0 50 +#define CLK_PWM1 51 +#define CLK_PWM2 52 +#define CLK_PWM3 53 +#define CLK_PWM4 54 +#define CLK_PWM5 55 +#define CLK_SD0 56 +#define CLK_SD1 57 +#define CLK_SD2 58 +#define CLK_SD3 59 +#define CLK_SENSOR 60 +#define CLK_SPEED_SENSOR 61 +#define CLK_SPI0 62 +#define CLK_SPI1 63 +#define CLK_SPI2 64 +#define CLK_SPI3 65 +#define CLK_THERMAL_SENSOR 66 +#define CLK_UART0 67 +#define CLK_UART1 68 +#define CLK_UART2 69 +#define CLK_UART3 70 +#define CLK_UART4 71 +#define CLK_UART5 72 +#define CLK_UART6 73 +#define CLK_VCE 74 +#define CLK_VDE 75 + +#define CLK_USB3_480MPLL0 76 +#define CLK_USB3_480MPHY0 77 +#define CLK_USB3_5GPHY 78 +#define CLK_USB3_CCE 79 +#define CLK_USB3_MAC 80 + +#define CLK_TIMER 83 + +#define CLK_HDMI_AUDIO 84 + +#define CLK_24M 85 + +#define CLK_EDP 86 + +#define CLK_24M_EDP 87 +#define CLK_EDP_PLL 88 +#define CLK_EDP_LINK 89 + +#define CLK_USB2H0_PLLEN 90 +#define CLK_USB2H0_PHY 91 +#define CLK_USB2H0_CCE 92 +#define CLK_USB2H1_PLLEN 93 +#define CLK_USB2H1_PHY 94 +#define CLK_USB2H1_CCE 95 + +#define CLK_DDR0 96 +#define CLK_DDR1 97 +#define CLK_DMM 98 + +#define CLK_ETH_MAC 99 +#define CLK_RMII_REF 100 + +#define CLK_NR_CLKS (CLK_RMII_REF + 1) + +#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */