From patchwork Thu Mar 15 16:35:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 131822 Delivered-To: patch@linaro.org Received: by 10.80.210.197 with SMTP id q5csp1698415edg; Thu, 15 Mar 2018 09:39:05 -0700 (PDT) X-Google-Smtp-Source: AG47ELu/ekELcGo+uHv4QMmpy2KhRMGpOLgZSht4HbJ5sSET5EuLqk40dT1bsE4NChdrJ2Ms9lSy X-Received: by 10.98.17.218 with SMTP id 87mr6556445pfr.160.1521131945116; Thu, 15 Mar 2018 09:39:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521131945; cv=none; d=google.com; s=arc-20160816; b=A4dGSNgqFrycmtvxvOkVfENA5TWyJPRr1G0ny+cf/NW0ZwlUOA/kQc6UhjnmvuMxjH pVbMk1uNw1Wcii1eEgWgtI1QAT9pvn4fTkZe06ax0hJWVJ37bZK2jPbw0N/XO/9qloeg PupqIrm+siiSGtqz0zBzLQPzL1OkErRQ83Q4pSNWAnZ+C0f34M0c9yD1fmG9PQCEzgp+ 8mPpP0XRU+F6YO4J13ur52pfeIcQEf96d7NogJRQZ3md6lTCULQTwtIfTHEZstOzR775 fB7f+sHdYcqFD40E7muH4IqnCOEOUdkXveOUHQjYuz9YUEVqGYjyPbYV6p/pxK+ZPMiK cIxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=ufrWkm6JmbhfagCdX0iY9Oqw++NyGc4fz21T45wh/PI=; b=gUisQy2LPY5asvx6QsalC37/XFMTxIfKnrJvd7dffkmP/EvZXtCH7WoM9GyIkWHrMu DGm5TzOLnJXFH2kFEoS2pFai5hau2NayaE2eHPP7Yb5kO/pDRbGlPVj8lHZfUk9oDQw+ H69vUGjQd4flXp2h25+lFWmN7dWJH9uHaMxx0lh6nsFT5fvv4sv0mVeW7pJqTNwIkFyd f+wHlBJREBXUiU8wpPBQ87WIE+FvLtJ6OIqoJ+qCgbh3cWCEuuzB0IIu1/U8IFWvKS2p wZYcB2Z1zVozxY8PhI5E0fpoF8TM1VOiqXGj/KsQu2pb0GmbAEG0/ndRqv5ZQUmVXk+o 1D5g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b10si3674019pgn.140.2018.03.15.09.39.04; Thu, 15 Mar 2018 09:39:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752471AbeCOQi7 (ORCPT + 28 others); Thu, 15 Mar 2018 12:38:59 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:39776 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752261AbeCOQiY (ORCPT ); Thu, 15 Mar 2018 12:38:24 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 7E21E4575D12F; Fri, 16 Mar 2018 00:38:09 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 16 Mar 2018 00:38:04 +0800 From: Shameer Kolothum To: , , CC: , , , , , , Shameer Kolothum , Robin Murphy , Joerg Roedel Subject: [PATCH v5 7/7] iommu/dma: Move PCI window region reservation back into dma specific path. Date: Thu, 15 Mar 2018 16:35:09 +0000 Message-ID: <20180315163509.17740-8-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20180315163509.17740-1-shameerali.kolothum.thodi@huawei.com> References: <20180315163509.17740-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This pretty much reverts commit 273df9635385 ("iommu/dma: Make PCI window reservation generic") by moving the PCI window region reservation back into the dma specific path so that these regions doesn't get exposed via the IOMMU API interface. With this change, the vfio interface will report only iommu specific reserved regions to the user space. Cc: Robin Murphy Cc: Joerg Roedel Signed-off-by: Shameer Kolothum --- drivers/iommu/dma-iommu.c | 54 ++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 29 deletions(-) -- 2.7.4 Acked-by: Robin Murphy diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index f05f3cf..ddcbbdb 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -167,40 +167,16 @@ EXPORT_SYMBOL(iommu_put_dma_cookie); * @list: Reserved region list from iommu_get_resv_regions() * * IOMMU drivers can use this to implement their .get_resv_regions callback - * for general non-IOMMU-specific reservations. Currently, this covers host - * bridge windows for PCI devices and GICv3 ITS region reservation on ACPI - * based ARM platforms that may require HW MSI reservation. + * for general non-IOMMU-specific reservations. Currently, this covers GICv3 + * ITS region reservation on ACPI based ARM platforms that may require HW MSI + * reservation. */ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) { - struct pci_host_bridge *bridge; - struct resource_entry *window; - - if (!is_of_node(dev->iommu_fwspec->iommu_fwnode) && - iort_iommu_msi_get_resv_regions(dev, list) < 0) - return; - - if (!dev_is_pci(dev)) - return; - - bridge = pci_find_host_bridge(to_pci_dev(dev)->bus); - resource_list_for_each_entry(window, &bridge->windows) { - struct iommu_resv_region *region; - phys_addr_t start; - size_t length; - - if (resource_type(window->res) != IORESOURCE_MEM) - continue; - start = window->res->start - window->offset; - length = window->res->end - window->res->start + 1; - region = iommu_alloc_resv_region(start, length, 0, - IOMMU_RESV_RESERVED); - if (!region) - return; + if (!is_of_node(dev->iommu_fwspec->iommu_fwnode)) + iort_iommu_msi_get_resv_regions(dev, list); - list_add_tail(®ion->list, list); - } } EXPORT_SYMBOL(iommu_dma_get_resv_regions); @@ -229,6 +205,23 @@ static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, return 0; } +static void iova_reserve_pci_windows(struct pci_dev *dev, + struct iova_domain *iovad) +{ + struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); + struct resource_entry *window; + unsigned long lo, hi; + + resource_list_for_each_entry(window, &bridge->windows) { + if (resource_type(window->res) != IORESOURCE_MEM) + continue; + + lo = iova_pfn(iovad, window->res->start - window->offset); + hi = iova_pfn(iovad, window->res->end - window->offset); + reserve_iova(iovad, lo, hi); + } +} + static int iova_reserve_iommu_regions(struct device *dev, struct iommu_domain *domain) { @@ -238,6 +231,9 @@ static int iova_reserve_iommu_regions(struct device *dev, LIST_HEAD(resv_regions); int ret = 0; + if (dev_is_pci(dev)) + iova_reserve_pci_windows(to_pci_dev(dev), iovad); + iommu_get_resv_regions(dev, &resv_regions); list_for_each_entry(region, &resv_regions, list) { unsigned long lo, hi;