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[209.132.180.67]) by mx.google.com with ESMTP id l13-v6si11545280pln.437.2018.03.24.06.33.59; Sat, 24 Mar 2018 06:33:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A69BPFY/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752522AbeCXNd4 (ORCPT + 28 others); Sat, 24 Mar 2018 09:33:56 -0400 Received: from mail-pl0-f68.google.com ([209.85.160.68]:40432 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752463AbeCXNdx (ORCPT ); Sat, 24 Mar 2018 09:33:53 -0400 Received: by mail-pl0-f68.google.com with SMTP id x4-v6so9120835pln.7 for ; Sat, 24 Mar 2018 06:33:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Uy+OnSE0HzTbPuBqcNNil7FWRqCLLGEQ+YyxDvuuSwQ=; b=A69BPFY/BrA5vCxJs+V4QgeIL4sK/vUJnkofQj1So1DEtwvWFqgZYLMWcnr3kkhPG2 NgeiXAms1ofJKRLLCchVeaRZVyQda3fV0eU2UZYXSyGcKIsPIsffhPVfkHIXfQ5zMdq1 XjCIqXRBfC7xSuicdQ7CbSFCq2BYLRoXiMv+o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Uy+OnSE0HzTbPuBqcNNil7FWRqCLLGEQ+YyxDvuuSwQ=; b=eZYVz4NnHm3scHhH6+WPZvKbkOSxD/GDUJnYTtzHS9KHpxKzkvrv0Vze0t2o2Iy3Ei xxw7j2RDcnlMGcWYE3mjQv68Ecu1BcQgzLsL8E9mLm4Y7u25YotvPFKHOwSmhwCQt16b P1+hdJjAqdNV9D+R2oyuY+2lObXWDNz9uCiGKO2LVFtt5m9yfon9olHyNf8zdfJnS+Ah dw77cX8yYUwxybT9YBRRtaIml9fcoe9DW2P1HL7ZUygQWU7sRwJ9gCapi2tPGgsau/rh pGx6b6SmIFXaKapzCJpSJRK/bvSXW69rvowfyO+2UmTuz2p5Bd/qKjnuN+pVY5RfIwgd /EBQ== X-Gm-Message-State: AElRT7Gn/mGjrbimMHVoJUNeclIv3pR01KWzOS7eLJtzs3v9EUNhomQ8 yJeoefbVVDluqYkIKEwIo2Dd X-Received: by 2002:a17:902:24a5:: with SMTP id w34-v6mr33349917pla.328.1521898432549; Sat, 24 Mar 2018 06:33:52 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7401:11e6:b12d:f551:4edc:7f21]) by smtp.gmail.com with ESMTPSA id a76sm4133980pfc.97.2018.03.24.06.33.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 24 Mar 2018 06:33:52 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v6 06/11] clk: actions: Add divider clock support Date: Sat, 24 Mar 2018 19:01:54 +0530 Message-Id: <20180324133159.4824-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180324133159.4824-1-manivannan.sadhasivam@linaro.org> References: <20180324133159.4824-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Actions Semi divider clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-divider.c | 94 +++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-divider.h | 75 +++++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 drivers/clk/actions/owl-divider.c create mode 100644 drivers/clk/actions/owl-divider.h -- 2.14.1 diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index 2d4aa8f35d90..5ce75df57e1a 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o clk-owl-y += owl-common.o clk-owl-y += owl-gate.o clk-owl-y += owl-mux.o +clk-owl-y += owl-divider.o diff --git a/drivers/clk/actions/owl-divider.c b/drivers/clk/actions/owl-divider.c new file mode 100644 index 000000000000..cddac00fe324 --- /dev/null +++ b/drivers/clk/actions/owl-divider.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL divider clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include + +#include "owl-divider.h" + +long owl_divider_helper_round_rate(struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long rate, + unsigned long *parent_rate) +{ + return divider_round_rate(&common->hw, rate, parent_rate, + div_hw->table, div_hw->width, + div_hw->div_flags); +} + +static long owl_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct owl_divider *div = hw_to_owl_divider(hw); + + return owl_divider_helper_round_rate(&div->common, &div->div_hw, + rate, parent_rate); +} + +unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long parent_rate) +{ + unsigned long val; + unsigned int reg; + + regmap_read(common->regmap, div_hw->reg, ®); + val = reg >> div_hw->shift; + val &= (1 << div_hw->width) - 1; + + return divider_recalc_rate(&common->hw, parent_rate, + val, div_hw->table, + div_hw->div_flags, + div_hw->width); +} + +static unsigned long owl_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct owl_divider *div = hw_to_owl_divider(hw); + + return owl_divider_helper_recalc_rate(&div->common, + &div->div_hw, parent_rate); +} + +int owl_divider_helper_set_rate(const struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long rate, + unsigned long parent_rate) +{ + unsigned long val; + unsigned int reg; + + val = divider_get_val(rate, parent_rate, div_hw->table, + div_hw->width, 0); + + regmap_read(common->regmap, div_hw->reg, ®); + reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift); + + regmap_write(common->regmap, div_hw->reg, + reg | (val << div_hw->shift)); + + return 0; +} + +static int owl_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct owl_divider *div = hw_to_owl_divider(hw); + + return owl_divider_helper_set_rate(&div->common, &div->div_hw, + rate, parent_rate); +} + +const struct clk_ops owl_divider_ops = { + .recalc_rate = owl_divider_recalc_rate, + .round_rate = owl_divider_round_rate, + .set_rate = owl_divider_set_rate, +}; diff --git a/drivers/clk/actions/owl-divider.h b/drivers/clk/actions/owl-divider.h new file mode 100644 index 000000000000..92d3e3d23967 --- /dev/null +++ b/drivers/clk/actions/owl-divider.h @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL divider clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_DIVIDER_H_ +#define _OWL_DIVIDER_H_ + +#include "owl-common.h" + +struct owl_divider_hw { + u32 reg; + u8 shift; + u8 width; + u8 div_flags; + struct clk_div_table *table; +}; + +struct owl_divider { + struct owl_divider_hw div_hw; + struct owl_clk_common common; +}; + +#define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ + { \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + .div_flags = _div_flags, \ + .table = _table, \ + } + +#define OWL_DIVIDER(_struct, _name, _parent, _reg, \ + _shift, _width, _table, _div_flags, _flags) \ + struct owl_divider _struct = { \ + .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \ + _div_flags, _table), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &owl_divider_ops, \ + _flags), \ + }, \ + } + +static inline struct owl_divider *hw_to_owl_divider(const struct clk_hw *hw) +{ + struct owl_clk_common *common = hw_to_owl_clk_common(hw); + + return container_of(common, struct owl_divider, common); +} + +long owl_divider_helper_round_rate(struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long rate, + unsigned long *parent_rate); + +unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long parent_rate); + +int owl_divider_helper_set_rate(const struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long rate, + unsigned long parent_rate); + +extern const struct clk_ops owl_divider_ops; + +#endif /* _OWL_DIVIDER_H_ */