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[209.132.180.67]) by mx.google.com with ESMTP id b7-v6si16062119pla.345.2018.05.03.23.01.26; Thu, 03 May 2018 23:01:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O5uXqN1s; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751674AbeEDGBX (ORCPT + 29 others); Fri, 4 May 2018 02:01:23 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:32854 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751598AbeEDGBU (ORCPT ); Fri, 4 May 2018 02:01:20 -0400 Received: by mail-wm0-f67.google.com with SMTP id x12-v6so5590543wmc.0 for ; Thu, 03 May 2018 23:01:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7B4c8Pjbxef6aiF7r7UqY+Hx8mO10Hq4pDea0nlrUGE=; b=O5uXqN1sLVzaKVr+4W1zsp9aSQSlrW3SKqe8J3g1SdCRx+O6rxSboZaY8y7xoOyjom zfZcWwjIb4eSuXhWfCXH1WdDaz+g0wger4fmxs6IDzUYtVvuhf0Runz1Nm0Mal6ybHOX RkkcIYCSrda7fkZXjRDzxb6Sqpp9IpKBSOmw8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7B4c8Pjbxef6aiF7r7UqY+Hx8mO10Hq4pDea0nlrUGE=; b=PibhjuMZD0rMfSLHOq6Aax/jLLfI1AmL3RyM0e/xtR4PrIQw//HhSlzUU5Lu6VCvbm YDoxLgfnUwGMKhkxlvLyzWG7VCEknpWtiQf8v9ShGQQBAKIXjcGiOlmTu24NFqDw4PSy eMR6WYf2bqo1n5+unbw7peVdIaTUB96M56dgZfB/6cIbjEqozThq12Mt5LmS8WQjQNiS rHsfdy92MLhcDEBcreGL8CoEPWqxOKAG1Y6/SyI0pdfepta1qulc8OuawosmLztdnfb/ Dydp+HzXT4aY2F3dTbfFrF7q2ufNIh5xCPDJf6aPR1tIt+9MXBkoAKdMFaEW3smpTuL2 l5tw== X-Gm-Message-State: ALQs6tCUT5jLZ5+z7kMTLDOWGK1lKnr18zQgrnpMeKR1gJacmEtVE0nq qrJnf4mpHt1S/qsE1QcKu3ilxA== X-Received: by 10.28.197.136 with SMTP id v130mr2437477wmf.135.1525413678961; Thu, 03 May 2018 23:01:18 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id i30-v6sm32411863wra.38.2018.05.03.23.01.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 May 2018 23:01:18 -0700 (PDT) From: Ard Biesheuvel To: linux-efi@vger.kernel.org, Ingo Molnar , Thomas Gleixner Cc: Yazen Ghannam , Ard Biesheuvel , linux-kernel@vger.kernel.org Subject: [PATCH 09/17] efi: Decode IA32/X64 MS Check structure Date: Fri, 4 May 2018 07:59:55 +0200 Message-Id: <20180504060003.19618-10-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180504060003.19618-1-ard.biesheuvel@linaro.org> References: <20180504060003.19618-1-ard.biesheuvel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yazen Ghannam The IA32/X64 MS Check structure varies from the other Check structures in the the bit positions of its fields, and it includes an additional "Error Type" field. Decode the MS Check structure in a separate function. Based on UEFI 2.7 Table 257. IA32/X64 MS Check Field Description. Signed-off-by: Yazen Ghannam Signed-off-by: Ard Biesheuvel --- drivers/firmware/efi/cper-x86.c | 55 ++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) -- 2.17.0 diff --git a/drivers/firmware/efi/cper-x86.c b/drivers/firmware/efi/cper-x86.c index 5e6716564dba..356b8d326219 100644 --- a/drivers/firmware/efi/cper-x86.c +++ b/drivers/firmware/efi/cper-x86.c @@ -57,6 +57,20 @@ #define CHECK_BUS_TIME_OUT BIT_ULL(32) #define CHECK_BUS_ADDR_SPACE(check) (((check) & GENMASK_ULL(34, 33)) >> 33) +#define CHECK_VALID_MS_ERR_TYPE BIT_ULL(0) +#define CHECK_VALID_MS_PCC BIT_ULL(1) +#define CHECK_VALID_MS_UNCORRECTED BIT_ULL(2) +#define CHECK_VALID_MS_PRECISE_IP BIT_ULL(3) +#define CHECK_VALID_MS_RESTARTABLE_IP BIT_ULL(4) +#define CHECK_VALID_MS_OVERFLOW BIT_ULL(5) + +#define CHECK_MS_ERR_TYPE(check) (((check) & GENMASK_ULL(18, 16)) >> 16) +#define CHECK_MS_PCC BIT_ULL(19) +#define CHECK_MS_UNCORRECTED BIT_ULL(20) +#define CHECK_MS_PRECISE_IP BIT_ULL(21) +#define CHECK_MS_RESTARTABLE_IP BIT_ULL(22) +#define CHECK_MS_OVERFLOW BIT_ULL(23) + enum err_types { ERR_TYPE_CACHE = 0, ERR_TYPE_TLB, @@ -111,17 +125,56 @@ static const char * const ia_check_bus_addr_space_strs[] = { "Other Transaction", }; +static const char * const ia_check_ms_error_type_strs[] = { + "No Error", + "Unclassified", + "Microcode ROM Parity Error", + "External Error", + "FRC Error", + "Internal Unclassified", +}; + static inline void print_bool(char *str, const char *pfx, u64 check, u64 bit) { printk("%s%s: %s\n", pfx, str, (check & bit) ? "true" : "false"); } +static void print_err_info_ms(const char *pfx, u16 validation_bits, u64 check) +{ + if (validation_bits & CHECK_VALID_MS_ERR_TYPE) { + u8 err_type = CHECK_MS_ERR_TYPE(check); + + printk("%sError Type: %u, %s\n", pfx, err_type, + err_type < ARRAY_SIZE(ia_check_ms_error_type_strs) ? + ia_check_ms_error_type_strs[err_type] : "unknown"); + } + + if (validation_bits & CHECK_VALID_MS_PCC) + print_bool("Processor Context Corrupt", pfx, check, CHECK_MS_PCC); + + if (validation_bits & CHECK_VALID_MS_UNCORRECTED) + print_bool("Uncorrected", pfx, check, CHECK_MS_UNCORRECTED); + + if (validation_bits & CHECK_VALID_MS_PRECISE_IP) + print_bool("Precise IP", pfx, check, CHECK_MS_PRECISE_IP); + + if (validation_bits & CHECK_VALID_MS_RESTARTABLE_IP) + print_bool("Restartable IP", pfx, check, CHECK_MS_RESTARTABLE_IP); + + if (validation_bits & CHECK_VALID_MS_OVERFLOW) + print_bool("Overflow", pfx, check, CHECK_MS_OVERFLOW); +} + static void print_err_info(const char *pfx, u8 err_type, u64 check) { u16 validation_bits = CHECK_VALID_BITS(check); + /* + * The MS Check structure varies a lot from the others, so use a + * separate function for decoding. + */ if (err_type == ERR_TYPE_MS) - return; + return print_err_info_ms(pfx, validation_bits, check); if (validation_bits & CHECK_VALID_TRANS_TYPE) { u8 trans_type = CHECK_TRANS_TYPE(check);