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[209.132.180.67]) by mx.google.com with ESMTP id u6-v6si15517576plz.461.2018.05.03.23.03.36; Thu, 03 May 2018 23:03:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IxH5uTuf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751950AbeEDGDe (ORCPT + 29 others); Fri, 4 May 2018 02:03:34 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:43974 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751561AbeEDGBQ (ORCPT ); Fri, 4 May 2018 02:01:16 -0400 Received: by mail-wr0-f196.google.com with SMTP id v15-v6so19755811wrm.10 for ; Thu, 03 May 2018 23:01:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eGeFWs/GhoS9om+2olzj/nHLTfhI4eGSHX+frG7YW3Q=; b=IxH5uTufGmFEb0gRJsEKsueFczs+UtJeuDSvL171H/dAfdTxTvtqGaY6Yh7160TAvZ bpXdAKGpo5nOn75i4Qg7KFvLxUcZyOGlRQwnEsjyQdOW833kWN3aOAUG+ZibRb9tB5q2 w0axDBh1LjBT7Ga/tHhIDAS/8/mpnlHiTM0QM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eGeFWs/GhoS9om+2olzj/nHLTfhI4eGSHX+frG7YW3Q=; b=nh5YokWK7f2LZygBLUTz0LRHIGvsCuPbQF3OhlWtZZmP96S+Xfb8VihnDPpAlPDNyF AGjy+151LrDxWYIUeoL1dpQXet5TwjcW0xCQinI1I6kTDQt7Wu6cJ0GyKAjRIp94wPA4 PW9BGoX6/oMyjLHwiBO/d6Uzg4qAxVRCxIGFkA+iZLOOmrxxY4YR5PemthkITThkPPEm BBFBaU3OJ2Wej+rzbTy4SJ1YpbVV7xU9loKUI6AyfxSJMTkQc4Q7+NPZgOncOCG6YoTM MXBKoNx5LFFG8/CkG7w0+D8/3osA3AbjHQMSnMm0t3k9JXq4/MTn8A5d0iE/fu6hQewK sujQ== X-Gm-Message-State: ALQs6tB1Hj3+wXlOimuno0iT+0eFYT6KezX8C08a7zpEm8poiRZ1WGbm tUpdUH/kkj7UOvpIi+CV3eOAXQ== X-Received: by 2002:adf:b90a:: with SMTP id k10-v6mr22654809wrf.283.1525413674969; Thu, 03 May 2018 23:01:14 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id i30-v6sm32411863wra.38.2018.05.03.23.01.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 May 2018 23:01:14 -0700 (PDT) From: Ard Biesheuvel To: linux-efi@vger.kernel.org, Ingo Molnar , Thomas Gleixner Cc: Yazen Ghannam , Ard Biesheuvel , linux-kernel@vger.kernel.org Subject: [PATCH 07/17] efi: Decode IA32/X64 Cache, TLB, and Bus Check structures Date: Fri, 4 May 2018 07:59:53 +0200 Message-Id: <20180504060003.19618-8-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180504060003.19618-1-ard.biesheuvel@linaro.org> References: <20180504060003.19618-1-ard.biesheuvel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yazen Ghannam Print the common fields of the Cache, TLB, and Bus check structures.The fields of these three check types are the same except for a few more fields in the Bus check structure. The remaining Bus check structure fields will be decoded in a following patch. Based on UEFI 2.7, Table 254. IA32/X64 Cache Check Structure Table 255. IA32/X64 TLB Check Structure Table 256. IA32/X64 Bus Check Structure Signed-off-by: Yazen Ghannam Signed-off-by: Ard Biesheuvel --- drivers/firmware/efi/cper-x86.c | 99 ++++++++++++++++++++++++++++++++- 1 file changed, 98 insertions(+), 1 deletion(-) -- 2.17.0 diff --git a/drivers/firmware/efi/cper-x86.c b/drivers/firmware/efi/cper-x86.c index 5438097b93ac..f70c46f7a4db 100644 --- a/drivers/firmware/efi/cper-x86.c +++ b/drivers/firmware/efi/cper-x86.c @@ -30,6 +30,25 @@ #define INFO_VALID_RESPONDER_ID BIT_ULL(3) #define INFO_VALID_IP BIT_ULL(4) +#define CHECK_VALID_TRANS_TYPE BIT_ULL(0) +#define CHECK_VALID_OPERATION BIT_ULL(1) +#define CHECK_VALID_LEVEL BIT_ULL(2) +#define CHECK_VALID_PCC BIT_ULL(3) +#define CHECK_VALID_UNCORRECTED BIT_ULL(4) +#define CHECK_VALID_PRECISE_IP BIT_ULL(5) +#define CHECK_VALID_RESTARTABLE_IP BIT_ULL(6) +#define CHECK_VALID_OVERFLOW BIT_ULL(7) + +#define CHECK_VALID_BITS(check) (((check) & GENMASK_ULL(15, 0))) +#define CHECK_TRANS_TYPE(check) (((check) & GENMASK_ULL(17, 16)) >> 16) +#define CHECK_OPERATION(check) (((check) & GENMASK_ULL(21, 18)) >> 18) +#define CHECK_LEVEL(check) (((check) & GENMASK_ULL(24, 22)) >> 22) +#define CHECK_PCC BIT_ULL(25) +#define CHECK_UNCORRECTED BIT_ULL(26) +#define CHECK_PRECISE_IP BIT_ULL(27) +#define CHECK_RESTARTABLE_IP BIT_ULL(28) +#define CHECK_OVERFLOW BIT_ULL(29) + enum err_types { ERR_TYPE_CACHE = 0, ERR_TYPE_TLB, @@ -52,11 +71,81 @@ static enum err_types cper_get_err_type(const guid_t *err_type) return N_ERR_TYPES; } +static const char * const ia_check_trans_type_strs[] = { + "Instruction", + "Data Access", + "Generic", +}; + +static const char * const ia_check_op_strs[] = { + "generic error", + "generic read", + "generic write", + "data read", + "data write", + "instruction fetch", + "prefetch", + "eviction", + "snoop", +}; + +static inline void print_bool(char *str, const char *pfx, u64 check, u64 bit) +{ + printk("%s%s: %s\n", pfx, str, (check & bit) ? "true" : "false"); +} + +static void print_err_info(const char *pfx, u8 err_type, u64 check) +{ + u16 validation_bits = CHECK_VALID_BITS(check); + + if (err_type == ERR_TYPE_MS) + return; + + if (validation_bits & CHECK_VALID_TRANS_TYPE) { + u8 trans_type = CHECK_TRANS_TYPE(check); + + printk("%sTransaction Type: %u, %s\n", pfx, trans_type, + trans_type < ARRAY_SIZE(ia_check_trans_type_strs) ? + ia_check_trans_type_strs[trans_type] : "unknown"); + } + + if (validation_bits & CHECK_VALID_OPERATION) { + u8 op = CHECK_OPERATION(check); + + /* + * CACHE has more operation types than TLB or BUS, though the + * name and the order are the same. + */ + u8 max_ops = (err_type == ERR_TYPE_CACHE) ? 9 : 7; + + printk("%sOperation: %u, %s\n", pfx, op, + op < max_ops ? ia_check_op_strs[op] : "unknown"); + } + + if (validation_bits & CHECK_VALID_LEVEL) + printk("%sLevel: %llu\n", pfx, CHECK_LEVEL(check)); + + if (validation_bits & CHECK_VALID_PCC) + print_bool("Processor Context Corrupt", pfx, check, CHECK_PCC); + + if (validation_bits & CHECK_VALID_UNCORRECTED) + print_bool("Uncorrected", pfx, check, CHECK_UNCORRECTED); + + if (validation_bits & CHECK_VALID_PRECISE_IP) + print_bool("Precise IP", pfx, check, CHECK_PRECISE_IP); + + if (validation_bits & CHECK_VALID_RESTARTABLE_IP) + print_bool("Restartable IP", pfx, check, CHECK_RESTARTABLE_IP); + + if (validation_bits & CHECK_VALID_OVERFLOW) + print_bool("Overflow", pfx, check, CHECK_OVERFLOW); +} + void cper_print_proc_ia(const char *pfx, const struct cper_sec_proc_ia *proc) { int i; struct cper_ia_err_info *err_info; - char newpfx[64]; + char newpfx[64], infopfx[64]; u8 err_type; if (proc->validation_bits & VALID_LAPIC_ID) @@ -87,6 +176,14 @@ void cper_print_proc_ia(const char *pfx, const struct cper_sec_proc_ia *proc) if (err_info->validation_bits & INFO_VALID_CHECK_INFO) { printk("%sCheck Information: 0x%016llx\n", newpfx, err_info->check_info); + + if (err_type < N_ERR_TYPES) { + snprintf(infopfx, sizeof(infopfx), "%s ", + newpfx); + + print_err_info(infopfx, err_type, + err_info->check_info); + } } if (err_info->validation_bits & INFO_VALID_TARGET_ID) {