From patchwork Tue May 22 16:34:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 136581 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1856223lji; Tue, 22 May 2018 09:37:20 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrANm14pks2XHMHoL/stMbdaiPk0V2Ol10+duZgD+kSlGRiBOu7vUPTH6yksQHprrTbUBeq X-Received: by 2002:a17:902:b68f:: with SMTP id c15-v6mr25387687pls.201.1527007040481; Tue, 22 May 2018 09:37:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527007040; cv=none; d=google.com; s=arc-20160816; b=Bs8RrQQBcptEa+03zUZr9BohbeRCwucFayalxcMvAhsibX2nFjTFFgyAr2mCV4/OLA kqfSXVaJdKu4xwshuoB6SO0rq28cAIbV0hs3r8iaU4A1KbYWFmHbm0VGDnawu2d+3Hsi eDiYDrkh60HKfHLHSzFQ3pMv76UkU0LSlfSTPRk/K1NPiLZStO2bY68hrYbgh7DKaYCv u9WVE1tmPr5vSUtlYax6WOzzglTgBGSMeGRK927Np5TwvXfVqj/Fzl79UD9yIkwVg6/B Egk+06R9Um+NgywqlmwBYqmJ7q8WmgL5gg7erfVxVWMjiEslCgepZCgnevLlbBs9EfDV Fo4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=lJ5098uzK326Ipm6uz2hXKqZE2Gslch8XuZpSgvbfj8=; b=p0sMThuipCjSO4m3NwYKdsVulfU7u6wt5nFMYfvnQv0DiaNQq7AWRLvKbpcyizWGE0 6KVuYRwwfeoNGlsVV2vm7gJsfYOOdajzPsnjUMMQ1QIlFoW3uxes9So1eTxzdrJvHIXv QgaWc4nVzZ//OwFtfIxhgeOCLpy5zUIjFl8S+10GhqqprNAEen3+ElDHCpA8AYsPunBs 7zwQ+Jgsjlo004MA85Ird2eCZvyKOzpo7pVk1Q4NgcbCvfVzXV0xv7rkJC8GDNWQxBFS iIwKjIzKaYRE5WHFeoSg3UMncLK155bI7nWyPvCV2Bk51FTdq6c51CWHUD+uGq10XBjx Wv5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=qUzpri3+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f15-v6si16162154plr.365.2018.05.22.09.37.20; Tue, 22 May 2018 09:37:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=qUzpri3+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752664AbeEVQhR (ORCPT + 30 others); Tue, 22 May 2018 12:37:17 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:34222 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751702AbeEVQfJ (ORCPT ); Tue, 22 May 2018 12:35:09 -0400 Received: by mail-wm0-f67.google.com with SMTP id a137-v6so17348982wme.1 for ; Tue, 22 May 2018 09:35:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lJ5098uzK326Ipm6uz2hXKqZE2Gslch8XuZpSgvbfj8=; b=qUzpri3+4Fb9xiA+H6VhPz85VbT8NhEjuzOxfGYEXg9dtPXcMgVCxVf6jZBsruvIAu bwuaeGP8XyKYH0WkXiGoJAa7doHSVaUsr3kQNVNlTAqRm+FfMu3/SqpcoxQxzX1hpRNP V96ldSLGsSmKrhLsGNaZnDKjEAzS4eQj5BOoZ2ZKL0CwHl2YJZh2sPuHc80b14RGzzX1 klXGVJ16pmkUMnPRQE1qzrFQP/+YNBV/spgaHR/Ut7oPnzW2oMFp0Qkc7K3CeHpi4Wfq gDBhr1h6P619VNwjeNg1O+0Qk1ccnNgp1TNzM3KuaqElyOXgTYQlNxQj1WoiYjXO2EZF sqqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lJ5098uzK326Ipm6uz2hXKqZE2Gslch8XuZpSgvbfj8=; b=Cok/3jAQzTVFFwkUBH1hO+bLJKoeJ8+ej1JI86+D2sfAj9P1FTRf4+qzc5PwD2C3T9 w/F9eWfkQkt1eZhZ+VYtkC45oHKy/BOACHsTs9sHoiMgdFJoeMzyLxBwGPpTATPVuh2E E6okR/9CWG2aw6QTUTxbB+r9s4xr8i9bziIiCGT4ZqfHqaW/sq01/3qpni2fiJ4kZ594 OfBh+rNLU5VFL8fEH7r64/HK4llOjTvMycPBiSPR7zESmo4rFaCMcOLFSGhRuvNmiYMu tvTckuvxrZmoxiaDuhKoNZqGFBDmFa0uQlAo4P2TmRQDKUTWal3BjpLflPw4abQMlbMO cdlg== X-Gm-Message-State: ALKqPwcHLWPcSl/mSBXJxnsRWq2Msm03EkNkLRQ1gnCpytX3O9+DwccI PHBtTZ4eW81EIunCi+Tt+UAoyA== X-Received: by 2002:a1c:512:: with SMTP id 18-v6mr1685264wmf.47.1527006907499; Tue, 22 May 2018 09:35:07 -0700 (PDT) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id h8-v6sm294062wmc.16.2018.05.22.09.35.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 May 2018 09:35:06 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , Michael Turquette , Stephen Boyd , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] dt-bindings: clock: add meson axg audio clock controller bindings Date: Tue, 22 May 2018 18:34:56 +0200 Message-Id: <20180522163457.13834-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180522163457.13834-1-jbrunet@baylibre.com> References: <20180522163457.13834-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export the clock ids dt-bindings usable by the consumers of the clock controller and add the documentation for the device tree bindings of the audio clock controller of the A113 based SoCs. Acked-by: Neil Armstrong Reviewed-by: Rob Herring Signed-off-by: Jerome Brunet --- .../bindings/clock/amlogic,axg-audio-clkc.txt | 56 +++++++++++++ include/dt-bindings/clock/axg-audio-clkc.h | 94 ++++++++++++++++++++++ 2 files changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt create mode 100644 include/dt-bindings/clock/axg-audio-clkc.h -- 2.14.3 diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt new file mode 100644 index 000000000000..61777ad24f61 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt @@ -0,0 +1,56 @@ +* Amlogic AXG Audio Clock Controllers + +The Amlogic AXG audio clock controller generates and supplies clock to the +other elements of the audio subsystem, such as fifos, i2s, spdif and pdm +devices. + +Required Properties: + +- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D +- reg : physical base address of the clock controller and length of + memory mapped region. +- clocks : a list of phandle + clock-specifier pairs for the clocks listed + in clock-names. +- clock-names : must contain the following: + * "pclk" - Main peripheral bus clock + may contain the following: + * "mst_in[0-7]" - 8 input plls to generate clock signals + * "slv_sclk[0-9]" - 10 slave bit clocks provided by external + components. + * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external + components. +- resets : phandle of the internal reset line +- #clock-cells : should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be +used in device tree sources. + +Example: + +clkc_audio: clock-controller@0 { + compatible = "amlogic,axg-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + resets = <&reset RESET_AUDIO>; +}; diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h new file mode 100644 index 000000000000..fd9c362099d9 --- /dev/null +++ b/include/dt-bindings/clock/axg-audio-clkc.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2018 Baylibre SAS. + * Author: Jerome Brunet + */ + +#ifndef __AXG_AUDIO_CLKC_BINDINGS_H +#define __AXG_AUDIO_CLKC_BINDINGS_H + +#define AUD_CLKID_SLV_SCLK0 9 +#define AUD_CLKID_SLV_SCLK1 10 +#define AUD_CLKID_SLV_SCLK2 11 +#define AUD_CLKID_SLV_SCLK3 12 +#define AUD_CLKID_SLV_SCLK4 13 +#define AUD_CLKID_SLV_SCLK5 14 +#define AUD_CLKID_SLV_SCLK6 15 +#define AUD_CLKID_SLV_SCLK7 16 +#define AUD_CLKID_SLV_SCLK8 17 +#define AUD_CLKID_SLV_SCLK9 18 +#define AUD_CLKID_SLV_LRCLK0 19 +#define AUD_CLKID_SLV_LRCLK1 20 +#define AUD_CLKID_SLV_LRCLK2 21 +#define AUD_CLKID_SLV_LRCLK3 22 +#define AUD_CLKID_SLV_LRCLK4 23 +#define AUD_CLKID_SLV_LRCLK5 24 +#define AUD_CLKID_SLV_LRCLK6 25 +#define AUD_CLKID_SLV_LRCLK7 26 +#define AUD_CLKID_SLV_LRCLK8 27 +#define AUD_CLKID_SLV_LRCLK9 28 +#define AUD_CLKID_DDR_ARB 29 +#define AUD_CLKID_PDM 30 +#define AUD_CLKID_TDMIN_A 31 +#define AUD_CLKID_TDMIN_B 32 +#define AUD_CLKID_TDMIN_C 33 +#define AUD_CLKID_TDMIN_LB 34 +#define AUD_CLKID_TDMOUT_A 35 +#define AUD_CLKID_TDMOUT_B 36 +#define AUD_CLKID_TDMOUT_C 37 +#define AUD_CLKID_FRDDR_A 38 +#define AUD_CLKID_FRDDR_B 39 +#define AUD_CLKID_FRDDR_C 40 +#define AUD_CLKID_TODDR_A 41 +#define AUD_CLKID_TODDR_B 42 +#define AUD_CLKID_TODDR_C 43 +#define AUD_CLKID_LOOPBACK 44 +#define AUD_CLKID_SPDIFIN 45 +#define AUD_CLKID_SPDIFOUT 46 +#define AUD_CLKID_RESAMPLE 47 +#define AUD_CLKID_POWER_DETECT 48 +#define AUD_CLKID_MST_A_MCLK 49 +#define AUD_CLKID_MST_B_MCLK 50 +#define AUD_CLKID_MST_C_MCLK 51 +#define AUD_CLKID_MST_D_MCLK 52 +#define AUD_CLKID_MST_E_MCLK 53 +#define AUD_CLKID_MST_F_MCLK 54 +#define AUD_CLKID_SPDIFOUT_CLK 55 +#define AUD_CLKID_SPDIFIN_CLK 56 +#define AUD_CLKID_PDM_DCLK 57 +#define AUD_CLKID_PDM_SYSCLK 58 +#define AUD_CLKID_MST_A_SCLK 79 +#define AUD_CLKID_MST_B_SCLK 80 +#define AUD_CLKID_MST_C_SCLK 81 +#define AUD_CLKID_MST_D_SCLK 82 +#define AUD_CLKID_MST_E_SCLK 83 +#define AUD_CLKID_MST_F_SCLK 84 +#define AUD_CLKID_MST_A_LRCLK 86 +#define AUD_CLKID_MST_B_LRCLK 87 +#define AUD_CLKID_MST_C_LRCLK 88 +#define AUD_CLKID_MST_D_LRCLK 89 +#define AUD_CLKID_MST_E_LRCLK 90 +#define AUD_CLKID_MST_F_LRCLK 91 +#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 +#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 +#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 +#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 +#define AUD_CLKID_TDMIN_A_SCLK 123 +#define AUD_CLKID_TDMIN_B_SCLK 124 +#define AUD_CLKID_TDMIN_C_SCLK 125 +#define AUD_CLKID_TDMIN_LB_SCLK 126 +#define AUD_CLKID_TDMOUT_A_SCLK 127 +#define AUD_CLKID_TDMOUT_B_SCLK 128 +#define AUD_CLKID_TDMOUT_C_SCLK 129 +#define AUD_CLKID_TDMIN_A_LRCLK 130 +#define AUD_CLKID_TDMIN_B_LRCLK 131 +#define AUD_CLKID_TDMIN_C_LRCLK 132 +#define AUD_CLKID_TDMIN_LB_LRCLK 133 +#define AUD_CLKID_TDMOUT_A_LRCLK 134 +#define AUD_CLKID_TDMOUT_B_LRCLK 135 +#define AUD_CLKID_TDMOUT_C_LRCLK 136 + +#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */