From patchwork Thu Jul 19 14:47:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 142346 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1823019ljj; Thu, 19 Jul 2018 07:48:19 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeqMrN+ju/cd4kEf6Ov01v5IzhBgcn1Al9yqdOMg+doDEOpgBzpiqDIi9YI7F3VXrpBTnic X-Received: by 2002:a17:902:e281:: with SMTP id cf1-v6mr10475748plb.293.1532011698946; Thu, 19 Jul 2018 07:48:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532011698; cv=none; d=google.com; s=arc-20160816; b=g54xdqbqLcE08xpgTYmALpPL9GZUm4M4p4AyZvMVghbcsdAGostaHY3o0e4XdJM/FO 9frJMkQdZYV2E+Oux6arsmXkO8pyaF9dPSpbJTqAYEOUTni3rdu6YkXeX2BP/odjssCy Wvi+dKWo5pdtPzQsgMZ/gAeCJquyknLFZZJe9QYF06G0vUX1mCLqTqTGk7Wova6y4pQh Wlt3NhfxFWOH2k/WkHi9IRN83rRdp0YrTFL9C8ZWRCg7GJ5pkVb6OOPBz8hp6keAG9q+ jPToPQwml+nkUQfKgS8hWEJNNFQrVnNFu8cuoms9KEfD2cE9xh63c3TofqgDEVusNPEe fLcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=fYp87y+gvIUQm7iTuOyLSql0Qx2qIrCHLqv3E9z5g+M=; b=rDiUfOD9aUrzuZsCfCpaCy/+qGfq0jm909yOga9I1eXhP7uOCaYgrJIcnxJkTXNC3P ED04Ufxk/fKYqHRfTFyfvVoqkxe3Z/DptsiYRWI6cMR1hBSxBS6vFG9dX8Uz2TiJCIKJ uGvJ01tNR+IKH+hetQKOWu8BuW1W4uWqO35N90WqWJVykRcMjZ939WpzwYp84oeJJUQn JVtA0j5hGX6+xJGkqCnlXMh1MHe8vc9monnDLGIBN7eHoZPv8o6j8wjjqvVTVoAmz9FW jEqK5IVE2waqP8X0kEVYoSb1/ex0K00RjTTSxLrN+yBOGTBt34mwneRYt2LS+ePwy20U LCCA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o8-v6si6235443pgr.461.2018.07.19.07.48.18; Thu, 19 Jul 2018 07:48:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731883AbeGSPbq (ORCPT + 31 others); Thu, 19 Jul 2018 11:31:46 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:46616 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731732AbeGSPbq (ORCPT ); Thu, 19 Jul 2018 11:31:46 -0400 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C730C9AAC6888; Thu, 19 Jul 2018 22:48:09 +0800 (CST) Received: from S00293818-DELL1.huawei.com (10.202.226.54) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.382.0; Thu, 19 Jul 2018 22:48:00 +0800 From: Salil Mehta To: CC: , , , , , , , Jian Shen Subject: [PATCH net-next 5/9] net: hns3: Use decimal for bit offset macros Date: Thu, 19 Jul 2018 15:47:02 +0100 Message-ID: <20180719144706.644-6-salil.mehta@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180719144706.644-1-salil.mehta@huawei.com> References: <20180719144706.644-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.226.54] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jian Shen Using hex for bit offsets is inconsistent with the rest of the file. Change them to decimal. Signed-off-by: Jian Shen Signed-off-by: Peng Li Signed-off-by: Salil Mehta --- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 24 +++++++++++----------- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 4 ++-- 2 files changed, 14 insertions(+), 14 deletions(-) -- 2.7.4 diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h index 940c159..219ffc7 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h @@ -579,13 +579,13 @@ enum hclge_mac_vlan_tbl_opcode { HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ }; -#define HCLGE_MAC_VLAN_BIT0_EN_B 0x0 -#define HCLGE_MAC_VLAN_BIT1_EN_B 0x1 -#define HCLGE_MAC_EPORT_SW_EN_B 0xc -#define HCLGE_MAC_EPORT_TYPE_B 0xb -#define HCLGE_MAC_EPORT_VFID_S 0x3 +#define HCLGE_MAC_VLAN_BIT0_EN_B 0 +#define HCLGE_MAC_VLAN_BIT1_EN_B 1 +#define HCLGE_MAC_EPORT_SW_EN_B 12 +#define HCLGE_MAC_EPORT_TYPE_B 11 +#define HCLGE_MAC_EPORT_VFID_S 3 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) -#define HCLGE_MAC_EPORT_PFID_S 0x0 +#define HCLGE_MAC_EPORT_PFID_S 0 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) struct hclge_mac_vlan_tbl_entry_cmd { u8 flags; @@ -601,7 +601,7 @@ struct hclge_mac_vlan_tbl_entry_cmd { u8 rsv2[6]; }; -#define HCLGE_VLAN_MASK_EN_B 0x0 +#define HCLGE_VLAN_MASK_EN_B 0 struct hclge_mac_vlan_mask_entry_cmd { u8 rsv0[2]; u8 vlan_mask; @@ -632,23 +632,23 @@ struct hclge_mac_mgr_tbl_entry_cmd { u8 rsv3[2]; }; -#define HCLGE_CFG_MTA_MAC_SEL_S 0x0 +#define HCLGE_CFG_MTA_MAC_SEL_S 0 #define HCLGE_CFG_MTA_MAC_SEL_M GENMASK(1, 0) -#define HCLGE_CFG_MTA_MAC_EN_B 0x7 +#define HCLGE_CFG_MTA_MAC_EN_B 7 struct hclge_mta_filter_mode_cmd { u8 dmac_sel_en; /* Use lowest 2 bit as sel_mode, bit 7 as enable */ u8 rsv[23]; }; -#define HCLGE_CFG_FUNC_MTA_ACCEPT_B 0x0 +#define HCLGE_CFG_FUNC_MTA_ACCEPT_B 0 struct hclge_cfg_func_mta_filter_cmd { u8 accept; /* Only used lowest 1 bit */ u8 function_id; u8 rsv[22]; }; -#define HCLGE_CFG_MTA_ITEM_ACCEPT_B 0x0 -#define HCLGE_CFG_MTA_ITEM_IDX_S 0x0 +#define HCLGE_CFG_MTA_ITEM_ACCEPT_B 0 +#define HCLGE_CFG_MTA_ITEM_IDX_S 0 #define HCLGE_CFG_MTA_ITEM_IDX_M GENMASK(11, 0) struct hclge_cfg_func_mta_item_cmd { __le16 item_idx; /* Only used lowest 12 bit */ diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index b84a140..aeae1ba 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -91,8 +91,8 @@ #define HCLGE_MISC_RESET_STS_REG 0x20700 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 #define HCLGE_GLOBAL_RESET_REG 0x20A00 -#define HCLGE_GLOBAL_RESET_BIT 0x0 -#define HCLGE_CORE_RESET_BIT 0x1 +#define HCLGE_GLOBAL_RESET_BIT 0 +#define HCLGE_CORE_RESET_BIT 1 #define HCLGE_FUN_RST_ING 0x20C00 #define HCLGE_FUN_RST_ING_B 0