From patchwork Tue Jul 24 11:45:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 142776 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp7166480ljj; Tue, 24 Jul 2018 04:46:43 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfPe2swxVl+esy1zy1lIYCpP5+yyQ/BmlnGOHBZePKV+BKu/l8BO6VJjmzQfV3Dq8souxYy X-Received: by 2002:a62:ec41:: with SMTP id k62-v6mr17286274pfh.206.1532432803409; Tue, 24 Jul 2018 04:46:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532432803; cv=none; d=google.com; s=arc-20160816; b=Rp1KOpNLuuxgJcnmj+b427VzjUcrR6Zvs0pA9ks0EKAkdCkk4v/1wVh0YA5nrxMBGX ZcwUF0nGfSMODPDtP1xQgVn0AmnS+aKA5ZZqtGxn4iXzDtxVY5o+T+2h8cR4tn3CnmaO D04LbLBwIxEMuumiSHwM8gTE5Uyc4nII3/LrdZgBvKNUrPRs+vg/w/77n07UXenO1x9M mvCJA/mPDCP0jHSjSBuFBzLQNuZZSvYhpaxAUZwJUW/ca+Jab+/mgp4/o+c0oF3NmXZx 3Hw/hG0DgBmhFhA1yPYHlZDqy2V+Prwn9bLMt1haQN6NmyLmg5Tt1lxgJIdlxsnhLBYR 7kwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=q2lkKDBL0yJzgIbex+6x3UQ1mTYL2lj5S11+frHD6yQ=; b=x3BpLOw6SYLmw4dYgiGIrBT8/Nu7Snd6hS3wZArFj7o4FGLDfZbXFgbzWSaSxd6/DY sBHY7efIFm9m7QXZr+g00diJSt43eGiY5joWQxXMMsICZk/4elj1YjHnEximsHRh0f2V cRB8zpIl7yJIB5Ad1RIZq8S0Q4RozVvMQ98W1JDN0mNRPwjC8H8Idix/3T1K+3NC69Q9 O+UIHh5MPB7kLEZOV8s61bKs6+0aBQm5DDFuWYX1aGV+UHS8aLVenI/3KA78J6OMckUf umzKqz+Ro+ua6vZKO/3BQdFeYXJJjCVAjwT0h7ocJaxZctuXgezFy8QNBv/GEtEO8U9/ ks9g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e12-v6si10798685pfn.322.2018.07.24.04.46.43; Tue, 24 Jul 2018 04:46:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388494AbeGXMwp (ORCPT + 31 others); Tue, 24 Jul 2018 08:52:45 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:10114 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388476AbeGXMwo (ORCPT ); Tue, 24 Jul 2018 08:52:44 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 04571103E3B15; Tue, 24 Jul 2018 19:46:35 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.382.0; Tue, 24 Jul 2018 19:46:29 +0800 From: Shameer Kolothum To: , CC: , , , , , , , , , , , Subject: [PATCH v2 4/4] perf/smmuv3: Add MSI irq support Date: Tue, 24 Jul 2018 12:45:15 +0100 Message-ID: <20180724114515.21764-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20180724114515.21764-1-shameerali.kolothum.thodi@huawei.com> References: <20180724114515.21764-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds support for MSI based counter overflow interrupt. Signed-off-by: Shameer Kolothum --- drivers/perf/arm_smmuv3_pmu.c | 105 +++++++++++++++++++++++++++++++++--------- 1 file changed, 84 insertions(+), 21 deletions(-) -- 2.7.4 diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index b3dc394..ca69813 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -94,6 +94,10 @@ #define SMMU_PMCG_IRQ_CFG2 0xE64 #define SMMU_PMCG_IRQ_STATUS 0xE68 +/* MSI config fields */ +#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) +#define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1 + #define SMMU_COUNTER_RELOAD BIT(31) #define SMMU_DEFAULT_FILTER_SEC 0 #define SMMU_DEFAULT_FILTER_SPAN 1 @@ -657,14 +661,89 @@ static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data) return IRQ_HANDLED; } +static void smmu_pmu_free_msis(void *data) +{ + struct device *dev = data; + + platform_msi_domain_free_irqs(dev); +} + +static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + phys_addr_t doorbell; + struct device *dev = msi_desc_to_dev(desc); + struct smmu_pmu *pmu = dev_get_drvdata(dev); + + doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; + doorbell &= MSI_CFG0_ADDR_MASK; + + writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); + writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1); + writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE, + pmu->reg_base + SMMU_PMCG_IRQ_CFG2); +} + +static void smmu_pmu_setup_msi(struct smmu_pmu *pmu) +{ + struct msi_desc *desc; + struct device *dev = pmu->dev; + int ret; + + /* Clear MSI address reg */ + writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); + + /* MSI supported or not */ + if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI)) + return; + + ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg); + if (ret) { + dev_warn(dev, "failed to allocate MSIs\n"); + return; + } + + desc = first_msi_entry(dev); + if (desc) + pmu->irq = desc->irq; + + /* Add callback to free MSIs on teardown */ + devm_add_action(dev, smmu_pmu_free_msis, dev); +} + +static int smmu_pmu_setup_irq(struct smmu_pmu *pmu) +{ + int irq, ret = -ENXIO; + + smmu_pmu_setup_msi(pmu); + + irq = pmu->irq; + if (irq) + ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq, + IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD, + "smmu-v3-pmu", pmu); + return ret; +} + static int smmu_pmu_reset(struct smmu_pmu *smmu_pmu) { + int ret; + /* Disable counter and interrupt */ writeq(smmu_pmu->counter_present_mask, smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0); writeq(smmu_pmu->counter_present_mask, smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0); + ret = smmu_pmu_setup_irq(smmu_pmu); + if (ret) { + dev_err(smmu_pmu->dev, "failed to setup irqs\n"); + return ret; + } + + /* Pick one CPU to be the preferred one to use */ + smmu_pmu->on_cpu = smp_processor_id(); + WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu))); + smmu_pmu_disable(&smmu_pmu->pmu); return 0; } @@ -738,26 +817,8 @@ static int smmu_pmu_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(dev, "Failed to get valid irq for smmu @%pa\n", - &mem_resource_0->start); - return irq; - } - - err = devm_request_irq(dev, irq, smmu_pmu_handle_irq, - IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD, - "smmu-pmu", smmu_pmu); - if (err) { - dev_err(dev, - "Unable to request IRQ%d for SMMU PMU counters\n", irq); - return err; - } - - smmu_pmu->irq = irq; - - /* Pick one CPU to be the preferred one to use */ - smmu_pmu->on_cpu = smp_processor_id(); - WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu))); + if (irq > 0) + smmu_pmu->irq = irq; smmu_pmu->num_counters = get_num_counters(smmu_pmu); smmu_pmu->counter_present_mask = GENMASK(smmu_pmu->num_counters - 1, 0); @@ -765,7 +826,9 @@ static int smmu_pmu_probe(struct platform_device *pdev) SMMU_PMCG_CFGR_SIZE_MASK) >> SMMU_PMCG_CFGR_SIZE_SHIFT; smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0); - smmu_pmu_reset(smmu_pmu); + err = smmu_pmu_reset(smmu_pmu); + if (err) + return err; err = cpuhp_state_add_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);