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[209.132.180.67]) by mx.google.com with ESMTP id i13-v6si14705366pgl.104.2018.07.31.20.40.34; Tue, 31 Jul 2018 20:40:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fx9EH1c0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732991AbeHAFX7 (ORCPT + 31 others); Wed, 1 Aug 2018 01:23:59 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:39856 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731051AbeHAFX6 (ORCPT ); Wed, 1 Aug 2018 01:23:58 -0400 Received: by mail-pf1-f196.google.com with SMTP id j8-v6so7106709pff.6 for ; Tue, 31 Jul 2018 20:40:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DFOLXivB49bmcMKwO1dGAMausF59FrddEHKCGI/sQ6k=; b=Fx9EH1c0ckh3gH32Q8FrFsIJh2rE2D+Z5yYgSsonPpIh2p9O480nTPV+S2Eo70D9uX TU6W60wuuq0yiNu6IxZr+OIYRNe7DOyURqffwPcN/W77znJLlBoOVLgid4QM2CaqyY36 ajYFwknEwx2vLig5xLbm2XT60ndGX/Ig9jo9I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DFOLXivB49bmcMKwO1dGAMausF59FrddEHKCGI/sQ6k=; b=b5kMjVA0AHUOqA6OzkipME01nrscpiW0StXmqLwTviCuyu+LlzZbrEfH2rI+Hq1KkL doGuh27MwZ8u/ESRDPel4mkmk06Ph4B71OQw6aSmvapa4peIAT1eOxJt/ZUgyfM55mrv YnJ975jQbF0CAov8Pd0Mt1xb9k7KFDNLRnLLShn1tLCWQYteviiyV490MLPD0wzEMiot Xr92PidCEQ/5OBWVwu/XLE5tOhehWEcnYgiv9HMDftrIvIJx4gfHTS0fSSbjZ0lkdEap XKoUd1rc4xmDdI3K5SwNDT9UxWlzyEynVP0kHTCSsLh9bt2FEF8NA0K1y73jODq5l70T 4V1w== X-Gm-Message-State: AOUpUlENeqIu+n8uTx8WryLr50QU+v0D/mkCa7r4IO9RlubZHYZlYFmX izU9nr5LIwVqUlqFNGVyB1tP X-Received: by 2002:a63:ce43:: with SMTP id r3-v6mr22750823pgi.439.1533094831456; Tue, 31 Jul 2018 20:40:31 -0700 (PDT) Received: from localhost.localdomain ([2405:204:730e:f0ae:ac4e:9cdd:28a2:4bf9]) by smtp.gmail.com with ESMTPSA id d19-v6sm34879545pgi.50.2018.07.31.20.40.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Jul 2018 20:40:30 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, lee.jones@linaro.org, arnd@arndb.de Cc: linux-clk@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, pn@denx.de, edgar.righi@lsitec.org.br, sravanhome@gmail.com, Manivannan Sadhasivam Subject: [PATCH v2 04/10] dt-bindings: reset: Add Actions Semi S900 SoC RMU support Date: Wed, 1 Aug 2018 09:09:09 +0530 Message-Id: <20180801033915.15880-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> References: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add RMU (Reset Management Unit) support for the Actions Semi S900 SoC which is a part of the Actions Semi Owl family series. Signed-off-by: Manivannan Sadhasivam --- .../bindings/reset/actions,owl-reset.txt | 33 ++++++++++ include/dt-bindings/reset/actions,s900-rmu.h | 65 +++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/actions,owl-reset.txt create mode 100644 include/dt-bindings/reset/actions,s900-rmu.h -- 2.17.1 diff --git a/Documentation/devicetree/bindings/reset/actions,owl-reset.txt b/Documentation/devicetree/bindings/reset/actions,owl-reset.txt new file mode 100644 index 000000000000..38e2c7051d86 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/actions,owl-reset.txt @@ -0,0 +1,33 @@ +Actions Semi Owl SoCs Reset Management Unit (RMU) +================================================= + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +The RMU registers are part of the system-controller block on Owl SoCs. + +Required properties: +- compatible: Should be "actions,s900-rmu" +- #reset-cells: Should be 1 + +All available resets are defined as preprocessor macros in corresponding +dt-bindings/reset/actions,s900-rmu.h header and can be used in device +tree sources. + +Parent node should have the following properties : +- compatible: "syscon", "simple-mfd" +- reg: physical base address of the system controller and length of + memory mapped region. + +Example: + + sysctrl: system-controller@e0160000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0xe0160000 0x0 0x1000>; + + rmu: reset-controller { + compatible = "actions,s900-rmu"; + #reset-cells = <1>; + }; + }; + diff --git a/include/dt-bindings/reset/actions,s900-rmu.h b/include/dt-bindings/reset/actions,s900-rmu.h new file mode 100644 index 000000000000..09e6dca46936 --- /dev/null +++ b/include/dt-bindings/reset/actions,s900-rmu.h @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +// +// Device Tree binding constants for Actions Semi S900 Reset Management Unit +// +// Copyright (c) 2018 Linaro Ltd. + +#ifndef _DT_BINDINGS_ACTIONS_S900_RESET_H +#define _DT_BINDINGS_ACTIONS_S900_RESET_H + +#define S900_RESET_CHIPID 0 +#define S900_RESET_CPU_SCNT 1 +#define S900_RESET_SRAMI 2 +#define S900_RESET_DDR_CTL_PHY 3 +#define S900_RESET_DMAC 4 +#define S900_RESET_GPIO 5 +#define S900_RESET_BISP_AXI 6 +#define S900_RESET_CSI0 7 +#define S900_RESET_CSI1 8 +#define S900_RESET_DE 9 +#define S900_RESET_DSI 10 +#define S900_RESET_GPU3D_PA 11 +#define S900_RESET_GPU3D_PB 12 +#define S900_RESET_HDE 13 +#define S900_RESET_I2C0 14 +#define S900_RESET_I2C1 15 +#define S900_RESET_I2C2 16 +#define S900_RESET_I2C3 17 +#define S900_RESET_I2C4 18 +#define S900_RESET_I2C5 19 +#define S900_RESET_IMX 20 +#define S900_RESET_NANDC0 21 +#define S900_RESET_NANDC1 22 +#define S900_RESET_SD0 23 +#define S900_RESET_SD1 24 +#define S900_RESET_SD2 25 +#define S900_RESET_SD3 26 +#define S900_RESET_SPI0 27 +#define S900_RESET_SPI1 28 +#define S900_RESET_SPI2 29 +#define S900_RESET_SPI3 30 +#define S900_RESET_UART0 31 +#define S900_RESET_UART1 32 +#define S900_RESET_UART2 33 +#define S900_RESET_UART3 34 +#define S900_RESET_UART4 35 +#define S900_RESET_UART5 36 +#define S900_RESET_UART6 37 +#define S900_RESET_HDMI 38 +#define S900_RESET_LVDS 39 +#define S900_RESET_EDP 40 +#define S900_RESET_USB2HUB 41 +#define S900_RESET_USB2HSIC 42 +#define S900_RESET_USB3 43 +#define S900_RESET_PCM1 44 +#define S900_RESET_AUDIO 45 +#define S900_RESET_PCM0 46 +#define S900_RESET_SE 47 +#define S900_RESET_GIC 48 +#define S900_RESET_DDR_CTL_PHY_AXI 49 +#define S900_RESET_CMU_DDR 50 +#define S900_RESET_DMM 51 +#define S900_RESET_HDCP2TX 52 +#define S900_RESET_ETHERNET 53 + +#endif /* _DT_BINDINGS_ACTIONS_S900_RESET_H */