From patchwork Fri Aug 3 09:56:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 143404 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp277723ljj; Fri, 3 Aug 2018 02:57:07 -0700 (PDT) X-Google-Smtp-Source: AAOMgpewQGxfU64GTmKr8TPXQc7Wn/vC716dCyF4Y7i382IlFBvw7ikDNCBh10kBziRnwcliz7OP X-Received: by 2002:a63:d74f:: with SMTP id w15-v6mr3064776pgi.306.1533290227570; Fri, 03 Aug 2018 02:57:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533290227; cv=none; d=google.com; s=arc-20160816; b=xPjFR/A8LbAPby+QfxSd9DhUNH8P9n+fC8JeOmtqwTkzuHjLLgII0si60CVVInV5pI UeZ5EL3kiD6ZmDPzQQKVQuoT6knlruetfyEzedc3PvvrWkrTFXS5vneyu1xYoXPNJaC6 Gt0k+7W7oXZqWzoxooaxEImU3qOyAMOUWENXoPAfmD/jw+onRx0wcIi2FOlfPkMiOvGG htMM6YBOftv1LmWKG5Doh/wpoZTwkcC5ja9wJI2SMMHlI/v7UZ6ZLRQcFbkHU17snTGS YuYWABD/1GUnfpuGj9FycL8mTPnrtX9gU3K6j7w2p5faFsZFasc5sNKfLPMvNroQaIvj LOXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=6aZz4SLbdqzjKSLvZ2h4v+lE+l5yEzRV3gxnuV9HKtE=; b=TRco1heAbxMIcXpCrWI4Hy5d2T4PhmQ8dQwmmLmfNPe8a6tA17WTcSymRNTo5u/Wh2 MoZ/LlR9ymP6ei7DPpObBPMosFDyJhMfE4/VDAgOPBPnffsZh9VOA/kWUNpYfry+WSn9 KYvjYQ9wQw3+CSFdEaAzsHLFuN+kdmdTf1mjsLlKtyNTdpZqzTTBibBBbXuCXn5/3UpB 9ckv7qll4Vl2JUeBgoBTl3GqIfDgh2lEKz4i41YOqHCBtOh/nPjTE+1lqEdXUpHqW+3B I0MitfM4f8r5ez1VQbSFZDW/pxF/uQ8ltaO1uBxc4TvwYJBbgkW3Gnb57laF/NpMFjYs fzbg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p2-v6si3302482plk.417.2018.08.03.02.57.07; Fri, 03 Aug 2018 02:57:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732605AbeHCLwi (ORCPT + 31 others); Fri, 3 Aug 2018 07:52:38 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:40178 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1732327AbeHCLwi (ORCPT ); Fri, 3 Aug 2018 07:52:38 -0400 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C1FCE17CDEC63; Fri, 3 Aug 2018 17:57:01 +0800 (CST) Received: from S00293818-DELL1.huawei.com (10.202.226.54) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.399.0; Fri, 3 Aug 2018 17:56:53 +0800 From: Salil Mehta To: CC: , , , , , , , Jian Shen Subject: [PATCH net-next 2/2] net: hns3: Refine the MSIX allocation for PF Date: Fri, 3 Aug 2018 10:56:31 +0100 Message-ID: <20180803095631.798-3-salil.mehta@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180803095631.798-1-salil.mehta@huawei.com> References: <20180803095631.798-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.226.54] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jian Shen The offset of msix number for roce is different between different revision id. We should get it from firmware, instead of a fix value. This patch refines the msix allocation, make it compatible. Signed-off-by: Jian Shen Signed-off-by: Peng Li Signed-off-by: Salil Mehta --- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 2 ++ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 8 ++++++-- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 3 +-- 3 files changed, 9 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h index 5cd22f9..cd0a4f2 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h @@ -358,6 +358,8 @@ struct hclge_pf_res_cmd { __le16 buf_size; __le16 msixcap_localid_ba_nic; __le16 msixcap_localid_ba_rocee; +#define HCLGE_MSIX_OFT_ROCEE_S 0 +#define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) #define HCLGE_PF_VEC_NUM_S 0 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) __le16 pf_intr_vector_number; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index a9b888f..fc813b7 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -932,6 +932,9 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev) hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; if (hnae3_dev_roce_supported(hdev)) { + hdev->roce_base_msix_offset = + hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), + HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S); hdev->num_roce_msi = hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); @@ -939,7 +942,8 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev) /* PF should have NIC vectors and Roce vectors, * NIC vectors are queued before Roce vectors. */ - hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET; + hdev->num_msi = hdev->num_roce_msi + + hdev->roce_base_msix_offset; } else { hdev->num_msi = hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), @@ -2037,7 +2041,7 @@ static int hclge_init_msi(struct hclge_dev *hdev) hdev->num_msi_left = vectors; hdev->base_msi_vector = pdev->irq; hdev->roce_base_vector = hdev->base_msi_vector + - HCLGE_ROCE_VECTOR_OFFSET; + hdev->roce_base_msix_offset; hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, sizeof(u16), GFP_KERNEL); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index dfa5c94..1528fb3 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -16,8 +16,6 @@ #define HCLGE_INVALID_VPORT 0xffff -#define HCLGE_ROCE_VECTOR_OFFSET 96 - #define HCLGE_PF_CFG_BLOCK_SIZE 32 #define HCLGE_PF_CFG_DESC_NUM \ (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) @@ -509,6 +507,7 @@ struct hclge_dev { u16 num_msi; u16 num_msi_left; u16 num_msi_used; + u16 roce_base_msix_offset; u32 base_msi_vector; u16 *vector_status; int *vector_irq;