From patchwork Thu Nov 8 17:50:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 150541 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1131048ljp; Thu, 8 Nov 2018 09:51:45 -0800 (PST) X-Google-Smtp-Source: AJdET5fuqdF5615lxUGoJt+wM89jLBEh92NTnYGtnUVziwuVyzsSLwRLvOoi5SKbghjsrTGbQf+h X-Received: by 2002:a17:902:292b:: with SMTP id g40-v6mr5139015plb.279.1541699505259; Thu, 08 Nov 2018 09:51:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541699505; cv=none; d=google.com; s=arc-20160816; b=adFYTMkwv8K7jtvOgl0z17UNHAdyCrNHbaYPxdCx/LKQm/THeTplUn94aY+NV7r0Ri PTrSpcFlIsAb/OBG52s4wVkrQLkP5l3cBT5O+x80CjupFbcFvMPNJYgBJkuzsmCpW2I7 3m8onxDfS5wWB1Luc1RA4QoQMk4zy3JuiVkq9Gcjcf8dZ/RbA5xAnlt55vmBeIANEOcG iBdmUNvKeYtTEMDx0Lr9QJ1GXfqeG3QdwdGsWYltWe7tCbxZXyK8CO1vl1NkapFNrTZz W8g3gkPiB1wvtzGRcuXhfDkBtMIQ9dxr+LOMywDWGIZBjD7a8UUHcxozf5iGGMryxVcf 0EgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=xRakDMzmhX1XuRrhweK14oRBxefzP4eSo6lUtz2qVOA=; b=tVUQFBeSAgYYuxL57BAggwOOAeXVIFZFKMY9TLurjDourrcyy8XQMEE5nNFUf5R8WM PtglVE+UDh4hfPCwKRUEjNgz1Hd9i8dTtXXRz6/iaPFz27d/6AeWO0CCihuFrhWHzmyf ZlelTrOMNK9FijAgCxgMfavj+ncg2Z7q4cPLyCAJcSuZppfRhqnXBVlvtZoAAiiUKPLn vR9ftqF/7la7TodPy2Iez4iKo+UluxH1iQ1o2qIdWjihhwk+RQ2HN/Fp3aIjxADQHMBf mmUD8kERz3xcNaLkeWmw+195UPXyINQ5TGHiF1ynMWy1/urDJ5LcMWdCG7bgEdW/57hp 4/Ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=0Dniz5pD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x12-v6si4793367pfn.111.2018.11.08.09.51.45; Thu, 08 Nov 2018 09:51:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=0Dniz5pD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727271AbeKID2R (ORCPT + 32 others); Thu, 8 Nov 2018 22:28:17 -0500 Received: from mail.kernel.org ([198.145.29.99]:40236 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726869AbeKID2R (ORCPT ); Thu, 8 Nov 2018 22:28:17 -0500 Received: from localhost.localdomain (unknown [171.76.98.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 44F2120827; Thu, 8 Nov 2018 17:51:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1541699500; bh=T+p6g0F8jAKv7ODkmKEX/ZT9E4g7uR/098U9KOe2h5o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0Dniz5pDUvP0JFhiznO4pm758z0qIOWltwFlUYRlqBrUo/f3cL1RrAZ3dGTpk6CNE SUJ+brScP39Zbl2rQoLqVJab0DOUuXYBk2w4W8M96NiXXSbBzyMAOmvsG4nc/znaPv 1TVIFkxH9wYSnZMAbrGR7NxTIDKphkdDY9o8OqfQ= From: Vinod Koul To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v3 01/18] arm64: dts: qcom: qcs404: add base dts files Date: Thu, 8 Nov 2018 23:20:32 +0530 Message-Id: <20181108175049.7090-2-vkoul@kernel.org> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20181108175049.7090-1-vkoul@kernel.org> References: <20181108175049.7090-1-vkoul@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add base dts files for QCS404 chipset along with cpu, timer, gcc and uart2 nodes. Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 175 +++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs404.dtsi -- 2.14.4 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi new file mode 100644 index 000000000000..b77d1198ba79 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, Linaro Limited + +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x0 0 0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-qcs404"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + + assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; + assigned-clock-rates = <19200000>; + }; + + blsp1_uart2: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b1000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "okay"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + clock-frequency = <19200000>; + + frame@b121000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = ; + reg = <0x0b123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; + reg = <0x0b124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = ; + reg = <0x0b125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = ; + reg = <0x0b126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = ; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = ; + reg = <0x0b128000 0x1000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +};