From patchwork Tue Nov 13 06:01:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 150920 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4013111ljp; Mon, 12 Nov 2018 22:01:10 -0800 (PST) X-Google-Smtp-Source: AJdET5d7TAVMdh4/8LN7vT39Ko2B+4o2/8FjxRS5ksMqMfgbObdy7YH3o3jf7MTjUn4E8fQ4UBTK X-Received: by 2002:a63:2f07:: with SMTP id v7mr3332648pgv.368.1542088870007; Mon, 12 Nov 2018 22:01:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542088869; cv=none; d=google.com; s=arc-20160816; b=TNUctA2+rSEJ9RQ/e3Vxx8vwMP/x0FgKma4dUhpvYmTiEezFw2mVqe6PdKTbsOQ7b6 trDcvuniqtsYmwVvEUddNNITPVnac//Fi033HiGJ7C2HfyJkZ1ZACJfZpb7M8U2Ie0pS icVJMVJFnxX833obKxpnSBp9flYrVHEQxEVU6N/IGvohAoaQZr0Af31BKAdj/woQMsNb O1Icy5e4lDDRiYH6yF94p3mGkloDZeXU8juY29uQZK50hhIvpPICQrNO4fMQ19XC82lL 4i+OivDUsENtAKVN2Ujk6xXsrsNYcBcOdTQlROgE3FF429SeCcGG6HeV9SkgDRXmf7W1 fhHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=1J2TiHKUBijIjPrVx3nB6w1N54AjJXwdsXUinG+MmK8=; b=oRdq+zc0+1AyjBpNVpuTECc41fPUDB/1P+WHY8Y2o6BBY+uH9y9ByQPwb5cLwRz/CE WAxUm5Aa/AlMQ93usgR+D/c1GGiNwDd6dvsoLztdJFg3HovOGVdws0Uw1cgYdV4TZ3FF VKS8mt5phnpcQnVlwrlkC3DAp52mKzZtIWTfLFnSsC47XFjFD83ZCbk/AJMCzQu8/wb7 sfyMYaSWlh7A5Kh11rsbuoOpDXjPlswez6vGlv8OejB87KmBaa1YTllziAo5n8/juBID Bhn4sQJp/0tgULArJUANRTk71gjT4VE7Mztv7hm2/PhVuLLTrjDbHuPraZPLr/T6T2I0 2Gkg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i34-v6si19307311pgb.71.2018.11.12.22.01.09; Mon, 12 Nov 2018 22:01:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732619AbeKMP5h (ORCPT + 32 others); Tue, 13 Nov 2018 10:57:37 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:45826 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731956AbeKMP5f (ORCPT ); Tue, 13 Nov 2018 10:57:35 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAD60WcJ067958; Tue, 13 Nov 2018 00:00:32 -0600 Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAD60W9G124217 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Nov 2018 00:00:32 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 13 Nov 2018 00:00:31 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 13 Nov 2018 00:00:32 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAD60Lu9017811; Tue, 13 Nov 2018 00:00:29 -0600 From: Vignesh R To: Tero Kristo , Rob Herring CC: Nishanth Menon , Mark Rutland , , , , Vignesh R , , Linus Walleij , Tony Lindgren Subject: [PATCH v2 2/4] arm64: dts: ti: k3-am65: Add pinctrl regions Date: Tue, 13 Nov 2018 11:31:09 +0530 Message-ID: <20181113060111.16374-3-vigneshr@ti.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181113060111.16374-1-vigneshr@ti.com> References: <20181113060111.16374-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tero Kristo Add pinctrl regions for the main and wkup mmr. The range for main pinctrl region contains a gap at offset 0x2e4, and because of this, the pinctrl range is split into two sections. Signed-off-by: Tero Kristo Signed-off-by: Vignesh R --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 + 3 files changed, 25 insertions(+) -- 2.19.1 diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index adcd6341e40c..f7c2a60d5c80 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -69,4 +69,20 @@ clock-frequency = <48000000>; current-speed = <115200>; }; + + main_pmx0: pinmux@11c000 { + compatible = "pinctrl-single"; + reg = <0x0 0x11c000 0x0 0x2e4>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_pmx1: pinmux@11c2e8 { + compatible = "pinctrl-single"; + reg = <0x0 0x11c2e8 0x0 0x24>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 8d7b47f9dfbf..19b46f40789b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -34,6 +34,14 @@ }; }; + wkup_pmx0: pinmux@4301c000 { + compatible = "pinctrl-single"; + reg = <0x4301c000 0x118>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + wkup_uart0: serial@42300000 { compatible = "ti,am654-uart"; reg = <0x42300000 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 3d4bf369d030..6fdfc7815811 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { model = "Texas Instruments K3 AM654 SoC";