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[209.132.180.67]) by mx.google.com with ESMTP id b24si1738049pgi.308.2019.02.08.02.14.27; Fri, 08 Feb 2019 02:14:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=kiIAwiTq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727547AbfBHKOZ (ORCPT + 31 others); Fri, 8 Feb 2019 05:14:25 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:40684 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726831AbfBHKOT (ORCPT ); Fri, 8 Feb 2019 05:14:19 -0500 Received: by mail-wm1-f68.google.com with SMTP id q21so2766504wmc.5 for ; Fri, 08 Feb 2019 02:14:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BRXDa+0TVxZcYoEC45CBTpx7rG6dgcS0Dc6O77EV4hs=; b=kiIAwiTqinORRZqbH7rVzo72b8E9f7tv8pZtF5tGQwUsd7Gijie4pObU2AcxROrqGE ah92UYjSBCvCLCkMCRk2pyWnIF2j/UPQXrVIo5qKlmJ1OOIzJNrVP9DVEX3khfojqWOh WqCoxR/OalA32yXCo0MB15dZ0sAID+kKoiHVI+QPoRiEQNWTQdURZ0bN0UjRoIyR5sjP +nSRRqR9RBa7PP1NBYMkheF7/DuIHATa9yEVHCa8+2AdM29qKF3xWjv+QibzF0aWu275 YW/v96Td7G81c/eHQuxSHeQBSUgfQYY43/EQWrVRRI0/UIRN7Y7RZ7237tX6XARSl8vJ R7LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BRXDa+0TVxZcYoEC45CBTpx7rG6dgcS0Dc6O77EV4hs=; b=fjsQtlH+wZwe7ndOYxmmtXQndW5AwNirO5ylvPUTPjT//TNmuJitGHfg/bEyJeZ1X5 hhUp+j+rLJQuoQDld2v2Jmu+btxnd/bBLmOdJAF51TQYcBWtyksqEad9JzLPU7a5oag4 wJHhw62YDSk4ieDcL3Ao5s6sStzStyrajDdskCNFMfgbrOzb/mO/iUm08rLPOG82ZpY4 cr8Ur8G+C7LzPvwT8JnK1xcZW3fCKuRASiZ9wLFdSFTr8QT+0YL2ecvYZWAeF6BoXvn6 knfBuzgPhFy09XLqDhzmHEp2FFwGmqHoYe90ejJMMK4Rvfta4GIuo0C965ky4oFew4XR Rm+A== X-Gm-Message-State: AHQUAuasqk6vETzBIbDB7g7LPBuPnkjuabDmGxitKeiraQWtaOsf1IeP UXSb1MSg79DJSO715XJlSj/xCA== X-Received: by 2002:a1c:c282:: with SMTP id s124mr10748554wmf.105.1549620857288; Fri, 08 Feb 2019 02:14:17 -0800 (PST) Received: from boomer.baylibre.com ([2a01:e35:2e9a:6060:2ed3:c463:803b:b085]) by smtp.googlemail.com with ESMTPSA id a62sm1901634wmf.47.2019.02.08.02.14.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 02:14:16 -0800 (PST) From: Jerome Brunet To: Kevin Hilman Cc: Jerome Brunet , linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong Subject: [PATCH 2/2] arm64: dts: meson: g12a: add peripheral clock controller Date: Fri, 8 Feb 2019 11:14:05 +0100 Message-Id: <20190208101405.25699-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190208101405.25699-1-jbrunet@baylibre.com> References: <20190208101405.25699-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the peripheral clock controller to the g12a SoC DT Signed-off-by: Jerome Brunet --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.20.1 diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 05ea750b8c16..701a02244e04 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -121,6 +121,19 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; + + hhi: system-controller@0 { + compatible = "amlogic,meson-gx-hhi-sysctrl", + "simple-mfd", "syscon"; + reg = <0 0 0 0x400>; + + clkc: clock-controller { + compatible = "amlogic,g12a-clkc"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + }; }; };