From patchwork Fri Feb 22 18:50:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 159060 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2070299jaa; Fri, 22 Feb 2019 10:51:13 -0800 (PST) X-Google-Smtp-Source: AHgI3IZXjXhvjWciOjZaoOYMWCDuFbAPBGXppi7fXoKxeT4vM2FfPUrkjosuvLpHb3ysLPsHJXIQ X-Received: by 2002:a65:43c1:: with SMTP id n1mr5418885pgp.248.1550861473039; Fri, 22 Feb 2019 10:51:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550861473; cv=none; d=google.com; s=arc-20160816; b=fYCR8k5PkRtPnhBTUv7mhaNoJpVHjazoGrEofX7xJbTB6WxXDMjd6U6zG7IlMC2JDK 7vjmAseaQj4FxtrmFsUkqPFg5vxTUTxE+kMOPHfi3XFBiF81/a+OZBrse6un+22tV+Sd fe/cGs8e1ZiWZUF6RbdxO/D8j8SyeGb7yX2za0FpAWwYgi878MCVvoECMTo926dgcS2f /nB7MQM7gRytoc+WBVjPGEj9YZRZ43tUhO6KdU3nkYBL0GvCgjG90b51mM8tEkVFqNBM fe8NiQeCXMZnIyl3H1yHt5Mp3ckLRnzLCDV+PXx/TAblBAHXkgqSQYTsfxiGdcCPF9QK vI3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=vI3FATtxi1AG2uFK415J44rPmcmeTuX+Ot7r45OyjfE=; b=rllP5vaISZ+I3xc0CEg4PqR+1btN9LHzyO755SjxGjfB23R3bhPe70tm6lDpKlvKKo XGe2kqo9zZY7vH2VhKmFaAoIJL22EAOvCARqe0ljylnWgf2bG0lWaJEVh6zyxP8+XEWr RN7p032bB/36WCNcmEQ6i+LG2u9zvS9hJ13ilHIhf8EbGQPzqfiUM7jrMCmEMCheJGZU lwwNn1HUu/s6x70xj3xpS9xKUOt7VUuXtbmOYSwdQ7zphSA+u5oXfsL04yYSs99714sZ FyAypNBSCOtWVQxhwudqlXkqy+LjXT4O84707w18A1LP4H2bBX2FrcafhlMXKuR6lMS3 o2jw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z23si1870592pgu.151.2019.02.22.10.51.12; Fri, 22 Feb 2019 10:51:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727554AbfBVSvL (ORCPT + 32 others); Fri, 22 Feb 2019 13:51:11 -0500 Received: from foss.arm.com ([217.140.101.70]:39414 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726368AbfBVSvK (ORCPT ); Fri, 22 Feb 2019 13:51:10 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 25CDF1688; Fri, 22 Feb 2019 10:51:10 -0800 (PST) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DF16C3F5C1; Fri, 22 Feb 2019 10:51:06 -0800 (PST) From: Will Deacon To: linux-arch@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Will Deacon , "Paul E. McKenney" , Benjamin Herrenschmidt , Michael Ellerman , Arnd Bergmann , Peter Zijlstra , Andrea Parri , Palmer Dabbelt , Daniel Lustig , David Howells , Alan Stern , Linus Torvalds , "Maciej W. Rozycki" , Paul Burton , Ingo Molnar , Yoshinori Sato , Rich Felker , Tony Luck Subject: [RFC PATCH 10/20] mips: Add unconditional mmiowb() to arch_spin_unlock() Date: Fri, 22 Feb 2019 18:50:16 +0000 Message-Id: <20190222185026.10973-11-will.deacon@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190222185026.10973-1-will.deacon@arm.com> References: <20190222185026.10973-1-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The mmiowb() macro is horribly difficult to use and drivers will continue to work most of the time if they omit a call when it is required. Rather than rely on driver authors getting this right, push mmiowb() into arch_spin_unlock() for mips. If this is deemed to be a performance issue, a subsequent optimisation could make use of ARCH_HAS_MMIOWB to elide the barrier in cases where no I/O writes were performned inside the critical section. Signed-off-by: Will Deacon --- arch/mips/include/asm/Kbuild | 1 - arch/mips/include/asm/io.h | 3 --- arch/mips/include/asm/mmiowb.h | 11 +++++++++++ arch/mips/include/asm/spinlock.h | 15 +++++++++++++++ 4 files changed, 26 insertions(+), 4 deletions(-) create mode 100644 arch/mips/include/asm/mmiowb.h -- 2.11.0 diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild index 5653b1e47dd0..f15d5db5dd67 100644 --- a/arch/mips/include/asm/Kbuild +++ b/arch/mips/include/asm/Kbuild @@ -13,7 +13,6 @@ generic-y += irq_work.h generic-y += local64.h generic-y += mcs_spinlock.h generic-y += mm-arch-hooks.h -generic-y += mmiowb.h generic-y += msi.h generic-y += parport.h generic-y += percpu.h diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 845fbbc7a2e3..29997e42480e 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -102,9 +102,6 @@ static inline void set_io_port_base(unsigned long base) #define iobarrier_w() wmb() #define iobarrier_sync() iob() -/* Some callers use this older API instead. */ -#define mmiowb() iobarrier_w() - /* * virt_to_phys - map virtual addresses to physical * @address: address to remap diff --git a/arch/mips/include/asm/mmiowb.h b/arch/mips/include/asm/mmiowb.h new file mode 100644 index 000000000000..a40824e3ef8e --- /dev/null +++ b/arch/mips/include/asm/mmiowb.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_MMIOWB_H +#define _ASM_MMIOWB_H + +#include + +#define mmiowb() iobarrier_w() + +#include + +#endif /* _ASM_MMIOWB_H */ diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index ee81297d9117..8a88eb265516 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -11,6 +11,21 @@ #include #include + +#include + +#define queued_spin_unlock queued_spin_unlock +/** + * queued_spin_unlock - release a queued spinlock + * @lock : Pointer to queued spinlock structure + */ +static inline void queued_spin_unlock(struct qspinlock *lock) +{ + /* This could be optimised with ARCH_HAS_MMIOWB */ + mmiowb(); + smp_store_release(&lock->locked, 0); +} + #include #endif /* _ASM_SPINLOCK_H */