From patchwork Thu Mar 21 09:59:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 160764 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp596360jan; Thu, 21 Mar 2019 03:01:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqw1DvUn21Vzx8vWkKXbz7Pm2oCSihdlGU5r/JpUqlYZ9m1qkqBY0IJ3BsyKKziHLKzMktw2 X-Received: by 2002:a63:9752:: with SMTP id d18mr2588155pgo.0.1553162484431; Thu, 21 Mar 2019 03:01:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553162484; cv=none; d=google.com; s=arc-20160816; b=WlpVjJBQdZav0eI3goLvBeu+9HwqJ99GWCStUl6HDgGj6iIuHoU4hVgE/iLmept+md 6dadJgc0BNkgIe2HU8I+8isPna5KObiBhvNNQ03PXXIOSBO4xbiJqikuYqIZT3mW8w9H AliowJ8uQKZwlN58oohrC2Q7aSJ+un5/nGd/c5sUBypPAaL7+cGgRYFcSkKJm3PnrfPR jER7d/vAxMgJhOd9HpVM3jnk/DX/9L4n/TguRJgjeDzCH6ClLozcZMclGrzYK2ZVfeT9 oPwGpagxBFjlRvAuKtXFEpJbWuuhZot+3y9Ms/WMIgGhJMgSOcS2d+KTLItAw5Av0wTn X/UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=BUFV/dDIIXZnSYWPXF7707YAbRpPqVyPPQ+Gegzd4eM=; b=lY8zi9tdjtucnxv5kzN8RSSoAhPeM4ZX9dAdQxT8wMhK5jLWrgSk8C0nxFNgGpEydM U3dCHOQ41tRQeRKXfprooUp5Q1AVPfJDTgop/VrsNNnqrutM1o0KTLrhY72DjkJ81aaX VqqOzvNfjFaZemaTLj5A1EEgJuh+/e1zvVrOeUEv7aWIFUfIddY4TM6BTxie8GjhwRsO 0VeI3pBYWNGFfd54RaWW0ccEm/ReyCGHT1HsBvGpIF5fU7MQGJVm2yuReprU2Dxz1PYA yeqVxGz6rW6tidO2OrdXGQ3XWGRb8RsOuSCkIRGgA9ucY+Sbz8KbRANLEglgcH503HDS Nrog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Juw73+f9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v5si3731758pgs.334.2019.03.21.03.01.24; Thu, 21 Mar 2019 03:01:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Juw73+f9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728436AbfCUKBW (ORCPT + 31 others); Thu, 21 Mar 2019 06:01:22 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:38258 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728214AbfCUKBV (ORCPT ); Thu, 21 Mar 2019 06:01:21 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2LA0dU9124623; Thu, 21 Mar 2019 05:00:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553162439; bh=BUFV/dDIIXZnSYWPXF7707YAbRpPqVyPPQ+Gegzd4eM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Juw73+f9Pk57JEr1BGWddtKe+oQNm4nIL+YrBQmenyd9zd5+3dGzpuF25d9GbYLhs ZSHqguFzNOvpoXuo6JzQsy81Q8QwTKWpwmVhhfOdFuOaciovmhnqsZcyZJU5SoJXSZ cpNuLmQMA9BsNzy2MPeBXckrwvtlb4jUOgcBj5Jg= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2LA0d4F093874 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 21 Mar 2019 05:00:39 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 21 Mar 2019 05:00:39 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Thu, 21 Mar 2019 05:00:39 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2LA0KOB014903; Thu, 21 Mar 2019 05:00:36 -0500 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Bjorn Helgaas , Gustavo Pimentel , Marc Zyngier CC: Kishon Vijay Abraham I , Jingoo Han , , , Subject: [PATCH v5 5/8] PCI: dwc: Add support to use non default msi_irq_chip Date: Thu, 21 Mar 2019 15:29:24 +0530 Message-ID: <20190321095927.7058-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190321095927.7058-1-kishon@ti.com> References: <20190321095927.7058-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Platforms using DesignWare IP use dw_pci_msi_bottom_irq_chip for configuring the MSI controller logic within the DesignWare IP. However certain platforms like Keystone (K2G) which uses DesignWare IP have their own MSI controller logic. For handling such platforms, the irqchip ops use msi_irq_ack(), msi_set_irq(), msi_clear_irq() callback functions. Add support to use different msi_irq_chip with default as dw_pci_msi_bottom_irq_chip. This is in preparation to get rid of msi_irq_ack(), msi_set_irq(), msi_clear_irq() and other Keystone specific dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-host.c | 5 ++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 25087d3c9a82..e28cb082f50d 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -245,7 +245,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, for (i = 0; i < nr_irqs; i++) irq_domain_set_info(domain, virq + i, bit + i, - &dw_pci_msi_bottom_irq_chip, + pp->msi_irq_chip, pp, handle_edge_irq, NULL, NULL); @@ -277,6 +277,9 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); + if (!pp->msi_irq_chip) + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, &dw_pcie_msi_domain_ops, pp); if (!pp->irq_domain) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 377f4c0b52da..6b0cea473ee7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -179,6 +179,7 @@ struct pcie_port { struct irq_domain *irq_domain; struct irq_domain *msi_domain; dma_addr_t msi_data; + struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_mask[MAX_MSI_CTRLS]; raw_spinlock_t lock;