From patchwork Fri Apr 5 13:59:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 161864 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp473794jan; Fri, 5 Apr 2019 07:01:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqzwK4vTDSfGb+N/zQeQ6EiSdl5K3aeIm+MAuxvTEah78eHB2nD/RpiX3IbD+fbXr4SCKZKz X-Received: by 2002:a63:3c19:: with SMTP id j25mr12339669pga.365.1554472892220; Fri, 05 Apr 2019 07:01:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554472892; cv=none; d=google.com; s=arc-20160816; b=KJeBU79ZRqN/Teo9Q6vmkNRcnze32VOtzKv2GvKQH5f2MDucImsaTKcptmDILb31kf IB1udXzH7Bi3fc61kkwjicT0o0Ff4R8/18xYsr2GIF8QPA0xwfQJrWxf7YEcD2GlXClc Mq9vu8mGUbJpZordP2rWnh6yZKTSDPaUc1w+4e2hsLt6FVsM1ePTzT00o6X+KVUyBYFV 5McRbt2Oh0ecUvGkZpJLi6gSVlqa8+pYzjyFTt0ddOP+weJj+Nfw75lCVMSXWGMoLzkt qbC0+/MAT9kJ0KncsB065G0mO7s3bUsYC0HNlgX0YxjOn30ku7/OWo8IbJbhBDCPrwMe AdlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=EhJGJ+x8OvxryuKIqEqb5PkKlc79cE+1XaUn4UpQ4zw=; b=P5VnvZbS9XeQ/NPHgQzv+jL9ulBuKlNow/lpX7cF/DLeK7v9OVg++XfvxWFJgVBMPZ /8aP6uKejgJknDfllNxIo26tlcTPzW4vj44ZG634rRgiKulvpYvu8fZ/Fp5Qqzhh4s5n HkhpmRddxsoozj/K4ymoC3CJLB9sL9ANs28f3dvh0Bm69GkemZsfBbUeHuvdAY0cvnhV qMMzd8mHIeFyMVgdKZzmLMKX4WAN37UrJwUcnSePCExRr5g3+gG5b+ShRKm+FRVOFul3 MWv+1DptXmaJ439uwams3HC9ILtVg2waXrCeIfqD6EDP70bO3FhgSN3IvrtwUN0TZwz4 lLkQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n74si2059127pfi.288.2019.04.05.07.01.31; Fri, 05 Apr 2019 07:01:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731462AbfDEOAg (ORCPT + 31 others); Fri, 5 Apr 2019 10:00:36 -0400 Received: from foss.arm.com ([217.140.101.70]:49432 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731437AbfDEOAa (ORCPT ); Fri, 5 Apr 2019 10:00:30 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 562AB1B55; Fri, 5 Apr 2019 07:00:30 -0700 (PDT) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 80DCA3F68F; Fri, 5 Apr 2019 07:00:26 -0700 (PDT) From: Will Deacon To: linux-arch@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Will Deacon , "Paul E. McKenney" , Benjamin Herrenschmidt , Michael Ellerman , Arnd Bergmann , Peter Zijlstra , Andrea Parri , Palmer Dabbelt , Daniel Lustig , David Howells , Alan Stern , Linus Torvalds , "Maciej W. Rozycki" , Paul Burton , Ingo Molnar , Yoshinori Sato , Rich Felker , Tony Luck , Mikulas Patocka , Akira Yokosawa , Luis Chamberlain , Nicholas Piggin Subject: [PATCH v2 11/21] mips/mmiowb: Add unconditional mmiowb() to arch_spin_unlock() Date: Fri, 5 Apr 2019 14:59:26 +0100 Message-Id: <20190405135936.7266-12-will.deacon@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190405135936.7266-1-will.deacon@arm.com> References: <20190405135936.7266-1-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The mmiowb() macro is horribly difficult to use and drivers will continue to work most of the time if they omit a call when it is required. Rather than rely on driver authors getting this right, push mmiowb() into arch_spin_unlock() for mips. If this is deemed to be a performance issue, a subsequent optimisation could make use of ARCH_HAS_MMIOWB to elide the barrier in cases where no I/O writes were performed inside the critical section. Acked-by: Paul Burton Signed-off-by: Will Deacon --- arch/mips/include/asm/Kbuild | 1 - arch/mips/include/asm/io.h | 3 --- arch/mips/include/asm/mmiowb.h | 11 +++++++++++ arch/mips/include/asm/spinlock.h | 15 +++++++++++++++ 4 files changed, 26 insertions(+), 4 deletions(-) create mode 100644 arch/mips/include/asm/mmiowb.h -- 2.11.0 diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild index bf39c2253ec8..87b86cdf126a 100644 --- a/arch/mips/include/asm/Kbuild +++ b/arch/mips/include/asm/Kbuild @@ -12,7 +12,6 @@ generic-y += irq_work.h generic-y += local64.h generic-y += mcs_spinlock.h generic-y += mm-arch-hooks.h -generic-y += mmiowb.h generic-y += msi.h generic-y += parport.h generic-y += percpu.h diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 845fbbc7a2e3..29997e42480e 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -102,9 +102,6 @@ static inline void set_io_port_base(unsigned long base) #define iobarrier_w() wmb() #define iobarrier_sync() iob() -/* Some callers use this older API instead. */ -#define mmiowb() iobarrier_w() - /* * virt_to_phys - map virtual addresses to physical * @address: address to remap diff --git a/arch/mips/include/asm/mmiowb.h b/arch/mips/include/asm/mmiowb.h new file mode 100644 index 000000000000..a40824e3ef8e --- /dev/null +++ b/arch/mips/include/asm/mmiowb.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_MMIOWB_H +#define _ASM_MMIOWB_H + +#include + +#define mmiowb() iobarrier_w() + +#include + +#endif /* _ASM_MMIOWB_H */ diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index ee81297d9117..8a88eb265516 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -11,6 +11,21 @@ #include #include + +#include + +#define queued_spin_unlock queued_spin_unlock +/** + * queued_spin_unlock - release a queued spinlock + * @lock : Pointer to queued spinlock structure + */ +static inline void queued_spin_unlock(struct qspinlock *lock) +{ + /* This could be optimised with ARCH_HAS_MMIOWB */ + mmiowb(); + smp_store_release(&lock->locked, 0); +} + #include #endif /* _ASM_SPINLOCK_H */