From patchwork Fri Apr 5 13:59:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 161865 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp473943jan; Fri, 5 Apr 2019 07:01:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqz0vx6I9Jipu2USDDT5samupzZcL5Jq2BhHLtKjuoFkKWEOhm4BEW0vekjJ2iUlxzP44s8X X-Received: by 2002:a63:ed10:: with SMTP id d16mr12163604pgi.75.1554472897189; Fri, 05 Apr 2019 07:01:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554472897; cv=none; d=google.com; s=arc-20160816; b=DFkgMFoyLGHmGKcJO9S/kSvJ0dxegecghT6XhADN6C6bi/wo8UEr8MoBY12TVCLkra o0vx1rfuTmPdAc+EFHaVLK1IbNwGzDS7n+h9qTrIoF+6aKQ6EGrasK11e1yQFBMA+KcY 4jP2UGs0OPhBmgtZqRSceqAreJGnMJv0gt2n7aZ2ponziF00wzBAMydY/FC3l0TsRt39 FEO+hzb58Y4iXTDjcGZJ4FYkPmcWSDK8kz8vxn08qyCylc4tMh5RVE2oJJotdnuWEWj2 mRXoIiA0ldQ6oliZwQ59P8UYWMY7SySPqEloguTETLkPzS5C5uGuqcPiRsqlH3gRtvaj ndEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=xuCsMpYVjx8DlofWVRWo4TBRH5JPwfe6AvkCsKWvfqg=; b=lM7sHKlY3zUllcDTmHVCg7bQMUiDx1qiovTnWjTSoOAMHeMDTnCOfBXxuTwFh/YJvu gfBrqBBUWCjKNusnqL0WU2kXUZmA2CJ2NW1lJfdnyfEQuT0sWmln+ojnuXYdropoBTwS bN7ckiHfQtMAF9IOCn8rNAyAKIbd2/9AgPL+XMDQ1idNvXzhX0SFJVakjnUuOwFDRQt7 2uP1tr01RFmqDpyawWoJTIepxkdagdCtbRQAQIY8119opvukg1zL2aragU7WXohAxOlk An+f0OJBMGgkA8/l82y7v+HSkPuNFVE76Yo6hMQqsAY7bqxzB1gl90v5Q7/cW7lI4wrQ utIQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l32si19039189pgm.130.2019.04.05.07.01.36; Fri, 05 Apr 2019 07:01:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731195AbfDEOBf (ORCPT + 31 others); Fri, 5 Apr 2019 10:01:35 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:49470 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731452AbfDEOAf (ORCPT ); Fri, 5 Apr 2019 10:00:35 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6DCC01A25; Fri, 5 Apr 2019 07:00:34 -0700 (PDT) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 97E873F68F; Fri, 5 Apr 2019 07:00:30 -0700 (PDT) From: Will Deacon To: linux-arch@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Will Deacon , "Paul E. McKenney" , Benjamin Herrenschmidt , Michael Ellerman , Arnd Bergmann , Peter Zijlstra , Andrea Parri , Palmer Dabbelt , Daniel Lustig , David Howells , Alan Stern , Linus Torvalds , "Maciej W. Rozycki" , Paul Burton , Ingo Molnar , Yoshinori Sato , Rich Felker , Tony Luck , Mikulas Patocka , Akira Yokosawa , Luis Chamberlain , Nicholas Piggin Subject: [PATCH v2 12/21] ia64/mmiowb: Add unconditional mmiowb() to arch_spin_unlock() Date: Fri, 5 Apr 2019 14:59:27 +0100 Message-Id: <20190405135936.7266-13-will.deacon@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190405135936.7266-1-will.deacon@arm.com> References: <20190405135936.7266-1-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The mmiowb() macro is horribly difficult to use and drivers will continue to work most of the time if they omit a call when it is required. Rather than rely on driver authors getting this right, push mmiowb() into arch_spin_unlock() for ia64. If this is deemed to be a performance issue, a subsequent optimisation could make use of ARCH_HAS_MMIOWB to elide the barrier in cases where no I/O writes were performed inside the critical section. Signed-off-by: Will Deacon --- arch/ia64/include/asm/Kbuild | 1 - arch/ia64/include/asm/io.h | 17 ----------------- arch/ia64/include/asm/mmiowb.h | 25 +++++++++++++++++++++++++ arch/ia64/include/asm/spinlock.h | 2 ++ 4 files changed, 27 insertions(+), 18 deletions(-) create mode 100644 arch/ia64/include/asm/mmiowb.h -- 2.11.0 diff --git a/arch/ia64/include/asm/Kbuild b/arch/ia64/include/asm/Kbuild index cabfe0280c33..11f191689c9e 100644 --- a/arch/ia64/include/asm/Kbuild +++ b/arch/ia64/include/asm/Kbuild @@ -5,7 +5,6 @@ generic-y += irq_work.h generic-y += kvm_para.h generic-y += mcs_spinlock.h generic-y += mm-arch-hooks.h -generic-y += mmiowb.h generic-y += preempt.h generic-y += trace_clock.h generic-y += vtime.h diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h index 1e6fef69bb01..a511d62d447a 100644 --- a/arch/ia64/include/asm/io.h +++ b/arch/ia64/include/asm/io.h @@ -113,20 +113,6 @@ extern int valid_mmap_phys_addr_range (unsigned long pfn, size_t count); */ #define __ia64_mf_a() ia64_mfa() -/** - * ___ia64_mmiowb - I/O write barrier - * - * Ensure ordering of I/O space writes. This will make sure that writes - * following the barrier will arrive after all previous writes. For most - * ia64 platforms, this is a simple 'mf.a' instruction. - * - * See Documentation/driver-api/device-io.rst for more information. - */ -static inline void ___ia64_mmiowb(void) -{ - ia64_mfa(); -} - static inline void* __ia64_mk_io_addr (unsigned long port) { @@ -161,7 +147,6 @@ __ia64_mk_io_addr (unsigned long port) #define __ia64_writew ___ia64_writew #define __ia64_writel ___ia64_writel #define __ia64_writeq ___ia64_writeq -#define __ia64_mmiowb ___ia64_mmiowb /* * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure @@ -296,7 +281,6 @@ __outsl (unsigned long port, const void *src, unsigned long count) #define __outb platform_outb #define __outw platform_outw #define __outl platform_outl -#define __mmiowb platform_mmiowb #define inb(p) __inb(p) #define inw(p) __inw(p) @@ -310,7 +294,6 @@ __outsl (unsigned long port, const void *src, unsigned long count) #define outsb(p,s,c) __outsb(p,s,c) #define outsw(p,s,c) __outsw(p,s,c) #define outsl(p,s,c) __outsl(p,s,c) -#define mmiowb() __mmiowb() /* * The address passed to these functions are ioremap()ped already. diff --git a/arch/ia64/include/asm/mmiowb.h b/arch/ia64/include/asm/mmiowb.h new file mode 100644 index 000000000000..297b85ac84a0 --- /dev/null +++ b/arch/ia64/include/asm/mmiowb.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_IA64_MMIOWB_H +#define _ASM_IA64_MMIOWB_H + +#include + +/** + * ___ia64_mmiowb - I/O write barrier + * + * Ensure ordering of I/O space writes. This will make sure that writes + * following the barrier will arrive after all previous writes. For most + * ia64 platforms, this is a simple 'mf.a' instruction. + */ +static inline void ___ia64_mmiowb(void) +{ + ia64_mfa(); +} + +#define __ia64_mmiowb ___ia64_mmiowb +#define mmiowb() platform_mmiowb() + +#include + +#endif /* _ASM_IA64_MMIOWB_H */ diff --git a/arch/ia64/include/asm/spinlock.h b/arch/ia64/include/asm/spinlock.h index afd0b3121b4c..5f620e66384e 100644 --- a/arch/ia64/include/asm/spinlock.h +++ b/arch/ia64/include/asm/spinlock.h @@ -73,6 +73,8 @@ static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock) { unsigned short *p = (unsigned short *)&lock->lock + 1, tmp; + /* This could be optimised with ARCH_HAS_MMIOWB */ + mmiowb(); asm volatile ("ld2.bias %0=[%1]" : "=r"(tmp) : "r"(p)); WRITE_ONCE(*p, (tmp + 2) & ~1); }