From patchwork Wed Apr 10 23:12:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 162049 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp6763283jan; Wed, 10 Apr 2019 16:13:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqwBafigVZMpnbh/QYKPLTCAuqf43YOzxkvMteLiofZmY0PjvLjvg8w+MK3IXNhgWx9TKpN8 X-Received: by 2002:a17:902:1c9:: with SMTP id b67mr25187706plb.158.1554937999899; Wed, 10 Apr 2019 16:13:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554937999; cv=none; d=google.com; s=arc-20160816; b=K5hg5pZjY/0ZXaFe+moFeF2q9IwmBLKsf8bDECnaHFLXAZVMj8JKk0abQyRujrppFo REGBPUOyl32/C9OpyeWWTfFR4TsdPv1OrCoNA3oS1TJLNTzkpnW8jZ6FrmjnDy7H0OOa z3xtvP0OE1+OFp2HE+VzHSYKKzc4r1Q4U7Cu9Sgh2WjI/vVyxMaojCXc+gROAoYgjFoe PSQ9HZ88MotSvsmEPk+a3/fDCY+g5OGVKrPoy8Og2tyfj+3ZQfktxs324xYhh+3hLWym ZWd9bkw60KybJvtijp3j9qi/1tXI/u8O4l486C99kJ+H76mkQIx3OEkOcpnYZROtYv4/ KRsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Yp1WfCiHn7GDlaVbiQRHbBwtPTYBLV8JF9ZFz6rWl54=; b=mhKLBhSYcUcM23r31bySfi5ICsB4qAUKIAWsiizS17ocYBWTPiF4/udQa64VE/naZX XlqHvDrNSqh2yUshquy5TblQr9Lo00edciPvPGBbmt2PS8lH1lgQXrqaot4SE5vuaqe+ G9p/mBSUV3Ix8zKh3Yg8BJjqWFe7Qk7zfUnx58HuiT4jB5SU/2YQr9yI7KEEjNTvRX9Q ic1dCCWfHzUzwRqIofDV+hZNKbfXD84afs9j2C4t3kkdBO8fzcAiAQGDRxH29zYwbMOb ApP+r6j7v9j+TxF3paLi7ScAv23dyygT81cQV5sK6S+55Do/UIjV78HNbdqDDQ/Y/VZt P6tw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c12si31425683pgq.390.2019.04.10.16.13.19; Wed, 10 Apr 2019 16:13:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726926AbfDJXNS (ORCPT + 31 others); Wed, 10 Apr 2019 19:13:18 -0400 Received: from foss.arm.com ([217.140.101.70]:33052 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726832AbfDJXM7 (ORCPT ); Wed, 10 Apr 2019 19:12:59 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A5D3A78; Wed, 10 Apr 2019 16:12:59 -0700 (PDT) Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.29.246]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E0C873F557; Wed, 10 Apr 2019 16:12:58 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2se.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton , Andre Przywara Subject: [v7 08/10] arm64: Always enable ssb vulnerability detection Date: Wed, 10 Apr 2019 18:12:35 -0500 Message-Id: <20190410231237.52506-9-jeremy.linton@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190410231237.52506-1-jeremy.linton@arm.com> References: <20190410231237.52506-1-jeremy.linton@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ssb detection logic is necessary regardless of whether the vulnerability mitigation code is built into the kernel. Break it out so that the CONFIG option only controls the mitigation logic and not the vulnerability detection. Signed-off-by: Jeremy Linton Reviewed-by: Andre Przywara Reviewed-by: Catalin Marinas Tested-by: Stefan Wahren --- arch/arm64/include/asm/cpufeature.h | 4 ---- arch/arm64/kernel/cpu_errata.c | 11 +++++++---- 2 files changed, 7 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index e505e1fbd2b9..6ccdc97e5d6a 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -638,11 +638,7 @@ static inline int arm64_get_ssbd_state(void) #endif } -#ifdef CONFIG_ARM64_SSBD void arm64_set_ssbd_mitigation(bool state); -#else -static inline void arm64_set_ssbd_mitigation(bool state) {} -#endif extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index fb8eb6c6088f..6958dcdabf7d 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -275,7 +275,6 @@ static int detect_harden_bp_fw(void) return 1; } -#ifdef CONFIG_ARM64_SSBD DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); int ssbd_state __read_mostly = ARM64_SSBD_KERNEL; @@ -346,6 +345,7 @@ void __init arm64_enable_wa2_handling(struct alt_instr *alt, *updptr = cpu_to_le32(aarch64_insn_gen_nop()); } +#ifdef CONFIG_ARM64_SSBD void arm64_set_ssbd_mitigation(bool state) { if (this_cpu_has_cap(ARM64_SSBS)) { @@ -370,6 +370,12 @@ void arm64_set_ssbd_mitigation(bool state) break; } } +#else +void arm64_set_ssbd_mitigation(bool state) +{ + pr_info_once("SSBD disabled by kernel configuration\n"); +} +#endif /* CONFIG_ARM64_SSBD */ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, int scope) @@ -467,7 +473,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, return required; } -#endif /* CONFIG_ARM64_SSBD */ static void __maybe_unused cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) @@ -759,14 +764,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors), }, #endif -#ifdef CONFIG_ARM64_SSBD { .desc = "Speculative Store Bypass Disable", .capability = ARM64_SSBD, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches = has_ssbd_mitigation, }, -#endif #ifdef CONFIG_ARM64_ERRATUM_1188873 { /* Cortex-A76 r0p0 to r2p0 */