From patchwork Tue Apr 30 11:38:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 163112 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3136077ill; Tue, 30 Apr 2019 05:05:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqxe33eh4OFjzN7XaGzr3Oglv8cvc4PU64vcx5kop/hsCL2vSUy+7l7vu4LFcxV3b0qat4h1 X-Received: by 2002:a17:902:12f:: with SMTP id 44mr24789871plb.193.1556625957256; Tue, 30 Apr 2019 05:05:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556625957; cv=none; d=google.com; s=arc-20160816; b=PxEJBL6wO5wTxxmeKQTkIkU87ONE2cta5BiniJr/rBV0EhGf51YweSBSrkst1lY9gd S1rSJWW2i1fPsDRPP8KblPg8K0kXwjq3f7/YYT69i4LTAHm0Dpip39RvzwWq9ypAHoEd eF+NRb1jYZo8sxcH8pDzMCVdv1iv7qfAjLc9CmsNu6ORewBA0/bUMt3yB5e6/u0PhXGJ VMjLxWodGxjtSbIq9vL2tIn54zE6neu6GmRgKnbBeYCGbtsZPbM1K16Li+a/3OHr+ATr i3e4OLSIoqMVvZ7fj2UPL3TF92jvqc16iooJCHezI84Kd9y+0dEPic0n705He+Ibhhtm f0fA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JLHEgpD1y0SFFpAbBBKc/Y3mDS4X0p5J2xXLoq/kY7Y=; b=du3TDi8ldrjm+eLWTNyTwYcgmaWXM/vqtfWXabjoujEzD/cxOvp06pzJJPIazyXJ8J U629ZdKOA2hMgp9ROviSWavQMdcUaDpXngc8gz4dCTYP9bkhS/IAlbPLq4UQRsb+qGec QiIXHLAZDcv+it5/KINlOq8WwhcSj9nO6kG9zo6wna/bsNg+nd36ghp33XwhOGjbll6O XSOQp6Xr99NrXWCUvWDeiDIDsPFUKk28L9E+whwR2EnEPjrEYXWtcU71EuirY+WlOlk1 pYdnuKhO1KqQ1x6zWAdGYHigqqh7dN1cLyu58Cqhspgilj17PJ9Z2yQ/IjxDCPBC4D+y S7HA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=I8FtWevV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e26si18524136pgb.368.2019.04.30.05.05.56; Tue, 30 Apr 2019 05:05:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=I8FtWevV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729002AbfD3MFz (ORCPT + 30 others); Tue, 30 Apr 2019 08:05:55 -0400 Received: from mail.kernel.org ([198.145.29.99]:49838 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728152AbfD3Llp (ORCPT ); Tue, 30 Apr 2019 07:41:45 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 776C72173E; Tue, 30 Apr 2019 11:41:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1556624505; bh=wSh+vCthql7JJLX/1r4HJUf6t9EDtOxHpRwPu8IoBQg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I8FtWevVyw97aTCtNl3nk9OCtNEZ3kOrjfd7U6Ob494sTNwX7PbwSi90JLPf2VPOk 7EIfTAqVNI9/QGTU6SaZRbfjP26wRLW1cKRNGZHd1Zk5luNChin23TDiUk/aQt06aX eO2OpBphuG5RA9n2ZlAgmsKCGoL5p/AdOkzLX4KY= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Marc Zyngier , Ard Biesheuvel , Russell King Subject: [PATCH 4.14 19/53] ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cache Date: Tue, 30 Apr 2019 13:38:26 +0200 Message-Id: <20190430113554.181129613@linuxfoundation.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190430113549.400132183@linuxfoundation.org> References: <20190430113549.400132183@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ard Biesheuvel commit e17b1af96b2afc38e684aa2f1033387e2ed10029 upstream. The EFI stub is entered with the caches and MMU enabled by the firmware, and once the stub is ready to hand over to the decompressor, we clean and disable the caches. The cache clean routines use CP15 barrier instructions, which can be disabled via SCTLR. Normally, when using the provided cache handling routines to enable the caches and MMU, this bit is enabled as well. However, but since we entered the stub with the caches already enabled, this routine is not executed before we call the cache clean routines, resulting in undefined instruction exceptions if the firmware never enabled this bit. So set the bit explicitly in the EFI entry code, but do so in a way that guarantees that the resulting code can still run on v6 cores as well (which are guaranteed to have CP15 barriers enabled) Cc: # v4.9+ Acked-by: Marc Zyngier Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/compressed/head.S | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -1393,7 +1393,21 @@ ENTRY(efi_stub_entry) @ Preserve return value of efi_entry() in r4 mov r4, r0 - bl cache_clean_flush + + @ our cache maintenance code relies on CP15 barrier instructions + @ but since we arrived here with the MMU and caches configured + @ by UEFI, we must check that the CP15BEN bit is set in SCTLR. + @ Note that this bit is RAO/WI on v6 and earlier, so the ISB in + @ the enable path will be executed on v7+ only. + mrc p15, 0, r1, c1, c0, 0 @ read SCTLR + tst r1, #(1 << 5) @ CP15BEN bit set? + bne 0f + orr r1, r1, #(1 << 5) @ CP15 barrier instructions + mcr p15, 0, r1, c1, c0, 0 @ write SCTLR + ARM( .inst 0xf57ff06f @ v7+ isb ) + THUMB( isb ) + +0: bl cache_clean_flush bl cache_off @ Set parameters for booting zImage according to boot protocol