From patchwork Wed May 1 13:58:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 163219 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp4554717ill; Wed, 1 May 2019 06:58:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqytPOvFL1dV8t2mfOVllQfZTsHN/pafPVaWKCGkcC23Tl4giv31zjj2cwWhtmyNK1Qq5gXR X-Received: by 2002:a65:6212:: with SMTP id d18mr74182898pgv.162.1556719135889; Wed, 01 May 2019 06:58:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556719135; cv=none; d=google.com; s=arc-20160816; b=Of09Q30mLvGKKkUA9hR1jM5qEIdECcMnkcipGDmJjhgNK9u8iBV44oBhI4oDg2Xwj9 d3T3SC/6JvOt9E+mjvNZhG/FrjUIc9rCHeaR9T2Txy/l+mBQF9xq97T0UtwwI1oXNIVo aDO/bnxUHHxK1o+BxL1KR4RUh8TUoiY0/QFDeFOjcQZwE+BoKrIP5dK3SMnorFEOHHCd AjAxB6SR/nc9vE0EBgjgT1kWT+XtuAf6W0I0Fd+uBzbtYzPTnLPYpjc/oENiQukkMObe idASYwd/XzFnH0bvzd7N59HI5QHKhkecTQAUheM2QsqLaj8IG+KWg7gdeAAJM2v59EbN /EQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=5YWucx5YeVmREPbqE3wTqTILeV6VyM7Q/wrTqluclv8=; b=t9NJYV3Wg/lOjx+WGqhJHznOG0vBeJmegDFWBIXxAKk7fFQ+VG8xE4cuJCZDFgvO3J wdqyOujauZk2ifZgJHbOOx94XQoeorWcsVN+0Gh0Zwn2CbCpExebrrbBpXBH8M7Ix75w JkRG8FlQQjVxolfRcslGoyAQmQ02yE9A1E5Vh/iIauLeheRw6KUhJY6gptZQmZmtQQcR D2WFdR3zDCmP5XQ2QteKe8y7pSMkssy6xFj764ImIl/a9PBlySuUfyjjhJzG0zWxiM9U t3dKK7D1B8L3vN/L3RXWcXy3JMFHdRL2dzzbbSCsCABWO6FXG9vZMmabaXohIi+GmVXa CRBA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u4si39884444pga.245.2019.05.01.06.58.55; Wed, 01 May 2019 06:58:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726724AbfEAN6y (ORCPT + 30 others); Wed, 1 May 2019 09:58:54 -0400 Received: from foss.arm.com ([217.140.101.70]:59732 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726423AbfEAN6w (ORCPT ); Wed, 1 May 2019 09:58:52 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B372BA78; Wed, 1 May 2019 06:58:51 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 64E6E3F5AF; Wed, 1 May 2019 06:58:49 -0700 (PDT) From: Julien Grall To: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org Cc: logang@deltatee.com, douliyangs@gmail.com, miquel.raynal@bootlin.com, marc.zyngier@arm.com, jason@lakedaemon.net, tglx@linutronix.de, joro@8bytes.org, robin.murphy@arm.com, bigeasy@linutronix.de, linux-rt-users@vger.kernel.org, Julien Grall Subject: [PATCH v3 6/7] irqchip/gic-v3-mbi: Don't map the MSI page in mbi_compose_m{b, s}i_msg() Date: Wed, 1 May 2019 14:58:23 +0100 Message-Id: <20190501135824.25586-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190501135824.25586-1-julien.grall@arm.com> References: <20190501135824.25586-1-julien.grall@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The functions mbi_compose_m{b, s}i_msg may be called from non-preemptible context. However, on RT, iommu_dma_map_msi_msg() requires to be called from a preemptible context. A recent patch split iommu_dma_map_msi_msg in two new functions: one that should be called in preemptible context, the other does not have any requirement. The GICv3 MSI driver is reworked to avoid executing preemptible code in non-preemptible context. This can be achieved by preparing the two MSI mappings when allocating the MSI interrupt. Signed-off-by: Julien Grall --- Changes in v2: - Rework the commit message to use imperative mood --- drivers/irqchip/irq-gic-v3-mbi.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) -- 2.11.0 diff --git a/drivers/irqchip/irq-gic-v3-mbi.c b/drivers/irqchip/irq-gic-v3-mbi.c index fbfa7ff6deb1..d50f6cdf043c 100644 --- a/drivers/irqchip/irq-gic-v3-mbi.c +++ b/drivers/irqchip/irq-gic-v3-mbi.c @@ -84,6 +84,7 @@ static void mbi_free_msi(struct mbi_range *mbi, unsigned int hwirq, static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *args) { + msi_alloc_info_t *info = args; struct mbi_range *mbi = NULL; int hwirq, offset, i, err = 0; @@ -104,6 +105,16 @@ static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, hwirq = mbi->spi_start + offset; + err = iommu_dma_prepare_msi(info->desc, + mbi_phys_base + GICD_CLRSPI_NSR); + if (err) + return err; + + err = iommu_dma_prepare_msi(info->desc, + mbi_phys_base + GICD_SETSPI_NSR); + if (err) + return err; + for (i = 0; i < nr_irqs; i++) { err = mbi_irq_gic_domain_alloc(domain, virq + i, hwirq + i); if (err) @@ -142,7 +153,7 @@ static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR); msg[0].data = data->parent_data->hwirq; - iommu_dma_map_msi_msg(data->irq, msg); + iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg); } #ifdef CONFIG_PCI_MSI @@ -202,7 +213,7 @@ static void mbi_compose_mbi_msg(struct irq_data *data, struct msi_msg *msg) msg[1].address_lo = lower_32_bits(mbi_phys_base + GICD_CLRSPI_NSR); msg[1].data = data->parent_data->hwirq; - iommu_dma_map_msi_msg(data->irq, &msg[1]); + iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), &msg[1]); } /* Platform-MSI specific irqchip */