From patchwork Wed Jul 24 19:21:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 169650 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp10698083ilk; Wed, 24 Jul 2019 13:23:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqw3lisiETRqhWKTHqFcsNszVQYK4vN3w3q36QxvX1OaD20JhNDOTK2zaG2Aj+a4af8PLDsI X-Received: by 2002:a17:90a:4806:: with SMTP id a6mr89723401pjh.38.1563999814059; Wed, 24 Jul 2019 13:23:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563999814; cv=none; d=google.com; s=arc-20160816; b=d4+W/OGXWTTIOgGuA4/a4T2ug6SrCgz/gaCZlhPul2f0RFxhkT+Yc4UUJEaLbFBz+1 ycFQMIfnMLjRA7ARmYxkJ47eByzCyj0mbvzOgJPzZKGHGjlW1iLLkDLYe7CYOwoPvlml 03jmLYdsYEikHMUrG9l0PglT44U1O2z/Y4FgkwK0QvmsVrdk73fJKO/1bRounw5JC6Se 88ci6ZyKso1JD3LCtNyJv/50tUH4dlidDeE/RwldsZHmglHB853l+AeKGvR4/+b+I9d7 AkYuRXk/SG+Gwv8m3RoPEo5S69VR2bVbTRJjnbaPsDIRWwxK4ml920pcT3HtWUEYxfmY 2Txg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SiN8sQ1sUXU64rpN5cED0idk/ZYYhiwAWj7CYskw9Eo=; b=U+DqsnUaY9yHIwC6NM4X3H9evv5b2fDMHh6DqCol41eYbYDCvSuoCcLrdDTqYDakRw EdUyXDzOQCNPwdoaKMr2KtVfGQjgjkXuB0D6GD1Fv7a48Efk9S7D4uIkK3kWM/z4pBtN 8VuL1vjsm6dLGeT1Ob+NvitJFwiUbEYvWmg+/PZlY9mIeY1ZR0qtNXCgQ2tLxL7t8RFB J6LeYxRoxWx7XtyQKwcbb+1E7es948NxDs56JZT26lrd2b6ObLON3dJLxJxKNsXFAL9z bBfdPnUYRXwsbwrM1AkF28baGZpeGyw/05qoDYciEaYw0eUHiixCXB0xVQNH3WGKvcJQ XvhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=KydtvRas; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o2si31359849pgp.288.2019.07.24.13.23.33; Wed, 24 Jul 2019 13:23:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=KydtvRas; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390414AbfGXTms (ORCPT + 29 others); Wed, 24 Jul 2019 15:42:48 -0400 Received: from mail.kernel.org ([198.145.29.99]:44578 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390409AbfGXTmq (ORCPT ); Wed, 24 Jul 2019 15:42:46 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 42AAD20665; Wed, 24 Jul 2019 19:42:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563997364; bh=aKEnaZ7Q19gHsX4lVgdncCYO5iiTFGDI+R4d4ch3Riw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KydtvRasS0UhI8RR1N1baE8p+rGN7EXj9Tu2NmNmxZ7LxIlGnIbRj6MhTVeizVMqL zo2ILwDeXd/v34VCjXSrUVYkvvV+7+tt2BKEUXSmoF9z22ELowcanD7OhXcW7KXUk4 KmRpOnhc6jSRkbC11DRcfslZKpfcKDVhzoHwE1G0= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Evan Green , Marc Gonzalez , Vivek Gautam , Niklas Cassel , Bjorn Andersson , Kishon Vijay Abraham I Subject: [PATCH 5.2 411/413] phy: qcom-qmp: Correct READY_STATUS poll break condition Date: Wed, 24 Jul 2019 21:21:42 +0200 Message-Id: <20190724191803.918536116@linuxfoundation.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190724191735.096702571@linuxfoundation.org> References: <20190724191735.096702571@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bjorn Andersson commit 885bd765963b42c380db442db7f1c0f2a26076fa upstream. After issuing a PHY_START request to the QMP, the hardware documentation states that the software should wait for the PCS_READY_STATUS to become 1. With the introduction of commit c9b589791fc1 ("phy: qcom: Utilize UFS reset controller") an additional 1ms delay was introduced between the start request and the check of the status bit. This greatly increases the chances for the hardware to actually becoming ready before the status bit is read. The result can be seen in that UFS PHY enabling is now reported as a failure in 10% of the boots on SDM845, which is a clear regression from the previous rare/occasional failure. This patch fixes the "break condition" of the poll to check for the correct state of the status bit. Unfortunately PCIe on 8996 and 8998 does not specify the mask_pcs_ready register, which means that the code checks a bit that's always 0. So the patch also fixes these, in order to not regress these targets. Fixes: 73d7ec899bd8 ("phy: qcom-qmp: Add msm8998 PCIe QMP PHY support") Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Cc: stable@vger.kernel.org Cc: Evan Green Cc: Marc Gonzalez Cc: Vivek Gautam Reviewed-by: Evan Green Reviewed-by: Niklas Cassel Reviewed-by: Marc Gonzalez Tested-by: Marc Gonzalez Signed-off-by: Bjorn Andersson Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Greg Kroah-Hartman --- drivers/phy/qualcomm/phy-qcom-qmp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1074,6 +1074,7 @@ static const struct qmp_phy_cfg msm8996_ .start_ctrl = PCS_START | PLL_READY_GATE_EN, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .mask_pcs_ready = PHYSTATUS, .mask_com_pcs_ready = PCS_READY, .has_phy_com_ctrl = true, @@ -1253,6 +1254,7 @@ static const struct qmp_phy_cfg msm8998_ .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .mask_pcs_ready = PHYSTATUS, .mask_com_pcs_ready = PCS_READY, }; @@ -1547,7 +1549,7 @@ static int qcom_qmp_phy_enable(struct ph status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; mask = cfg->mask_pcs_ready; - ret = readl_poll_timeout(status, val, !(val & mask), 1, + ret = readl_poll_timeout(status, val, val & mask, 1, PHY_INIT_COMPLETE_TIMEOUT); if (ret) { dev_err(qmp->dev, "phy initialization timed-out\n");